AURIX™ Forum Discussions

[User9635]

Hello Support,

For Aurix 2G, there is ALM2[1] -- Safety Mechanism: Bus-level Memory Protection Unit / Register Access Protection

Also in User Manual the following Section :
5.3.4.17 CPU Memory Protection Registers

For Section "5.3.4.17 CPU Memory Protection Registers", execution violation due to range mismatch causes "Class 1 — Internal Protection Traps" if MPU is enabled

The questions are :

1> If ALM2[1] is activated, then will the Section "5.3.4.17" MPU violation will cause SMU Alarm instead of usual CPU Class 1 Trap?

2> Is
"ALM2[1] -- Safety Mechanism: Bus-level Memory Protection Unit / Register Access Protection" feature
available even when CPU MPU is not enabled by setting bit CPU_SYSCON.PROTEN=0 -- Bit 1 of CPU CSFR SYSCON Register?





Best Regards

[NeMa_4793301]

#1: The SMU reaction to ALM2[1] is in addition to the CPU trap. If you configure the alarm reaction for ALM2[1] to NMI, you'll see the CPU trap followed immediately by the SMU alarm in the CSA chain.

#2: The Bus-level Memory Protection is a separate safety mechanism, unaffected by the CPU MPU PROTEN setting.