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AURIX™ Forum Discussions

User22033
Level 1
Level 1
Hello,

I would be very grateful for an explanation on how the access to CSFR via the XBAR is realized?

This is the only Information I could find in the available documents
"A CPU must access its own CSFR registers using MTCR and MFCR instructions. CSFR registers of other CPUs may
be accessed using load and store instructions via the XBAR_SRI.SFR registers of any CPU may only be accessed
using load and store instructions via XBAR_SRI. Currently the overlay control and the access protection registers
of CPUx are mapped into CPUx SFR address range." [Infineon-AURIX_TC3xx_Part1-UserManual-v01_00-EN.pdf p.304 chapter 5.3.6.1.2 CFSR and SFR base Location]

Thanks in advance
Best regards
Konrad
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4 Replies
Darren_Galpin
Employee
Employee
First solution authored First like received
Hi - what this really means is that to access the registers of say CPU1 from CPU0, you have to go via the SRI interconnect - there is a missing space in "XBAR_SRI.SFR", it should read "XBAR_SRI. SFR". You do a load or store instruction to the CPU1 target address from CPU0 - the access then goes onto the interconnect and to the target CPU.

Cheers,

Darren
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User22033
Level 1
Level 1
Thanks for the useful explanation!

I have open questions regarding to your explanations:

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"to access the registers of say CPU1 from CPU0, you have to go via the SRI interconnect "

1. For the communication via the SRI interconnect which changes have to be made to the corresponding Registers ?
In my example Code "Blinky_LED_1_KIT_TC387_TFT" I have found the following match when I search for XBAR

Ifx_SRC_SRCR XBAR0; /**< \brief 30, SRI Domain 0 Service Request*/

typedef union
{
Ifx_UReg_32Bit U; /**< \brief Unsigned access */
Ifx_SReg_32Bit I; /**< \brief Signed access */
Ifx_SRC_SRCR_Bits B; /**< \brief Bitfield access */
} Ifx_SRC_SRCR;

typedef struct _Ifx_SRC_SRCR_Bits
{
Ifx_UReg_32Bit SRPN:8; /**< \brief [7:0] Service Request Priority Number (rw) */
Ifx_UReg_32Bit reserved_8:2; /**< \brief [9:8] \internal Reserved */
Ifx_UReg_32Bit SRE:1; /**< \brief [10:10] Service Request Enable (rw) */
Ifx_UReg_32Bit TOS:3; /**< \brief [13:11] Type of Service Control (rw) */
Ifx_UReg_32Bit reserved_14:2; /**< \brief [15:14] \internal Reserved */
Ifx_UReg_32Bit ECC:5; /**< \brief [20:16] Error Correction Code (rwh) */
Ifx_UReg_32Bit reserved_21:3; /**< \brief [23:21] \internal Reserved */
Ifx_UReg_32Bit SRR:1; /**< \brief [24:24] Service Request Flag (rh) */
Ifx_UReg_32Bit CLRR:1; /**< \brief [25:25] Request Clear Bit (w) */
Ifx_UReg_32Bit SETR:1; /**< \brief [26:26] Request Set Bit (w) */
Ifx_UReg_32Bit IOV:1; /**< \brief [27:27] Interrupt Trigger Overflow Bit (rh) */
Ifx_UReg_32Bit IOVCLR:1; /**< \brief [28:28] Interrupt Trigger Overflow Clear Bit (w) */
Ifx_UReg_32Bit SWS:1; /**< \brief [29:29] SW Sticky Bit (rh) */
Ifx_UReg_32Bit SWSCLR:1; /**< \brief [30:30] SW Sticky Clear Bit (w) */
Ifx_UReg_32Bit reserved_31:1; /**< \brief [31:31] \internal Reserved */
} Ifx_SRC_SRCR_Bits;

It seems to me as if the XBAR SRI interconnect communication is managed by Interrupt Router. Is that correct? If so by which event is the interrupt triggered?

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"You do a load or store instruction to the CPU1 target address from CPU0 - the access then goes onto the interconnect and to the target CPU."

2. How do these load and store instructions syntactically look like? Are the load or store instructions done with inline assembly?

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

I think a code example would help me a lot.


Best regards
Konrad
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Darren_Galpin
Employee
Employee
First solution authored First like received
The interrupt router and the XBAR are different. The interrupt router takes interrupt requests from the various blocks, arbitrates, and presents the winner to the target to deal with. The XBAR is the place and route in the interconnect for transactions. It has registers, because you can read error status for example, but it primarily routes transactions between agents. If CPU0 wants to read a CPU1 register, you just get CPU0 to read from the CPU1 register address - CPU0 will send it to the interconnect, and the interconnect will send it to the correct CPU/target and return the response.

The register you highlighted is for where the XBAR0 issues an interrupt, usually because it has detected an error response somewhere. This register then configures how the interrupt router arbitrates it.

I don't have code examples to give you (outside of my expertise), but the instructions can be in inline assembly, or if you are compiling a c-program, could simply be a call to get a value from a register located in CPU1, assuming that the code is being executed on CPU0.
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User22033
Level 1
Level 1
okay now i get it. And it has worked out perfectly for my application!


Thank you Darren, you made my day!
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