AURIX™ Forum Discussions

[User22683]

Some software functionality that is safety-critical should be executed by a lock-stepped processor in a TC27x microcontroller.

• In the TC27x, there are two processors with checker cores, TC1.6P and TC1.6.E. I am wondering, what would be the procs/cons of choosing either of the two for such executions?
  
• During start-up after a cold-reset, if only CPU0's lock-stepped mode is enabled, does this interfere with the initialization sequence shown in the attachment (copied from ap32201_TC2xx_StartupAndInitialization.pdf) ?
  
• During start-up after a cold-reset, if only CPU1's lock-stepped mode is enabled, does this interfere with the initialization sequence shown in the attachment(copied from ap32201_TC2xx_StartupAndInitialization.pdf) ?
  
• During start-up after a cold-reset, if both CPU0 and CPU1's lock-stepped modes are enabled, how might the initialization sequence look like?
  

[NeMa_4793301 · Accepted solution]

#1: TC1.6P is a performance core, offering a 25-30% speed improvement due to a 6-stage pipeline (vs. 4 for the TC1.6E efficiency core). The performance core does consume more current.
#2-4: Lockstep has no impact on performance or the initialization sequence.

[User22683]

Thanks for your helpful feedback