AURIX MCU : Lockstep Core

[User050592]

I have a question regarding lockstep. Which areas are duplicated exactly in lockstep core? is the program counter register also duplicated? or is it common for both master and checker core?

What are failure modes covered with Lockstep safety mechanism?

Thanks in advance!!

[Di_W]

Dear User,

Hope to answer your question from https://community.infineon.com/t5/AURIX/What-is-the-compare-in-Lockstep-from-AURIX/td-p/314155

dw

[User050592]

Thank you very much for the answer.

Unfortunately I didn't get fully clarified. I would like to know whether the fault in the program counter register is detected in the Lockstep core.

[Di_W]

Dear User,

Sorry there is only limited info on this topic. From my understanding, the PC fault will lead a watchdog alarm /reset that is another way to protect the system.

dw

[User050592]

Thank you for your feedback.

For. e.g. If the AURIX is executing safety software and if the Program counter is incremented by 8 instead of 4, how this will be detected by Watchdog? do you mean internal watchdog or external watchdog? I think both of them will not be able to find it out.  

[Di_W]

Yes, watchdog will handle that code jump to unexpected position and not to serve the dog in time. Like you said,  if PC jump a little, watchdog maybe not able to find out.  

[Di_W · Accepted solution]

Dear User,

Please refer to AURIX TC3xx Safety Manual v2.0, note that CSFR includes PC register.

4.2.1.1.2 Monitoring Concept

Lockstep CPU
Depending on the variant, a TC3xx offers up to 4 lockstep CPU. The LS-CPU monitoring is based on hardware
redundancy with online monitoring of the outputs. The logic covered by this hardware redundancy is called the
CPU area of duplication and comprises:
• TriCore TC1.62P core
• CPU SFR and CSFR
......

dw

[User050592]

Thank you for the answer.  I just saw in the user manual, its included. Thank you again.