Aug 31, 2020
08:46 AM
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Aug 31, 2020
08:46 AM
Hello everyone,
I'm working with the KIT_A2G_TC397XA_TFT and i'm wondering if there any code example to work with the LCD XGA Display, i have used one from the HighTec Development Plataform example but it seems it doesn't work well after a Cold (initial) power-on reset.
Thanks for your attention!
I'm working with the KIT_A2G_TC397XA_TFT and i'm wondering if there any code example to work with the LCD XGA Display, i have used one from the HighTec Development Plataform example but it seems it doesn't work well after a Cold (initial) power-on reset.
Thanks for your attention!
7 Replies
Sep 01, 2020
12:32 AM
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Sep 01, 2020
12:32 AM
Make sure that you have programmed a valid BMHD with your used reset address. Look in the debugger which value the PC contains.
Sep 02, 2020
06:57 AM
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Sep 02, 2020
06:57 AM
MoD wrote:
Make sure that you have programmed a valid BMHD with your used reset address. Look in the debugger which value the PC contains.
Hi, thanks for answering!
I have not change the BMHD address from the example I started from, everything else in project works as expected after a cold reset except for the LCD screen.
Where can I found information about how to change the BMHD in order to solve this issue?
Thanks for the help!
Sep 03, 2020
04:15 AM
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Sep 03, 2020
04:15 AM
I expected that the complete project not work after cold reset but you wrote only the LCD don't work. Therefore I expect that there is no problem with the BMHD.
You can find a running demo code here (including LCD):
https://myicp.infineon.com/sites/microcontrollers-aurix_customer_doc/Lists/MyICP%20Customer%20Docume...
You can find a running demo code here (including LCD):
https://myicp.infineon.com/sites/microcontrollers-aurix_customer_doc/Lists/MyICP%20Customer%20Docume...
Mar 02, 2021
07:06 PM
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Mar 02, 2021
07:06 PM
Hi MoD
Could you share me the example?
Could you share me the example?
Mar 03, 2021
02:35 AM
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Mar 03, 2021
02:35 AM
Please see here for registration on myicp, then you can download it from there:
https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricor...
https://www.infineon.com/cms/en/product/microcontroller/32-bit-tricore-microcontroller/32-bit-tricor...
Mar 11, 2021
04:49 AM
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Mar 11, 2021
04:49 AM
Hi alexhuang,
hopefully you did some steps forward since last post.
I did some equal experiments with the same result. You can literally manipulate
the whole display but if you restart the application, the pixels are sometimes not what they are supposed to be.
This could be also an issue with the timing during communication between the AURIX and the also mounted FPGA or
it could be an issue with the implementation inside the FPGA itself.
From the AURIX programming point of view, you could only search for the display interface implementation and look
for possible timing issues. Maybe you could also investigate it by using a scope. If there is an issue, you should easily find it.
Maybe you could also delay the display output a little bit until all cores are working properly and maybe also wait until the FPGA is up and running.
It could be possible that the FPGA is not waiting for the AURIX to be ready, and grabs therefore whatever is on the line during startup.
Lot of possibilities 😉
I think all this is a matter of implementation. You should not be afraid of asking HighTec directly, if it comes to implementation details regarding AURIX/FPGA communication.
Regards,
Jens
hopefully you did some steps forward since last post.
I did some equal experiments with the same result. You can literally manipulate
the whole display but if you restart the application, the pixels are sometimes not what they are supposed to be.
This could be also an issue with the timing during communication between the AURIX and the also mounted FPGA or
it could be an issue with the implementation inside the FPGA itself.
From the AURIX programming point of view, you could only search for the display interface implementation and look
for possible timing issues. Maybe you could also investigate it by using a scope. If there is an issue, you should easily find it.
Maybe you could also delay the display output a little bit until all cores are working properly and maybe also wait until the FPGA is up and running.
It could be possible that the FPGA is not waiting for the AURIX to be ready, and grabs therefore whatever is on the line during startup.
Lot of possibilities 😉
I think all this is a matter of implementation. You should not be afraid of asking HighTec directly, if it comes to implementation details regarding AURIX/FPGA communication.
Regards,
Jens
Mar 11, 2021
05:49 AM
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Mar 11, 2021
05:49 AM
Here you can find a customized demo output of the kit.
[video]https://youtu.be/2UquPMui9og[/video]
Regards,
Jens
[video]https://youtu.be/2UquPMui9og[/video]
Regards,
Jens