ASCLIN Spi mode 0 / 3

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beamk
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Hello,

regarding the ASCLIN module the question came up how to configure it to be used with devices that need SPI mode 0.

If I see it correctly only the clock polarity can be changed, but not the clock phase.

Thus typically the connected slave device would need to understand SPI mode 1 or 2.

Is there a way to change the clock phase?

(Using iLLD)

Best
beamk

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David_R
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Hello @beamk 

That's correct, for mode 0 the data sampled on rising edge and shifted out on the falling edge, the first plot is corresponding to a SPI mode 0 transfer, due the logic analyzer maybe it can't be noticed the details, but the settings were set to decode this mode.

Let me do it again using an oscilloscope to confirm it, but with you results we can conclude that the ASCLIN SPI works with mode 1 and 3 which makes sense to try to cover the most sensors, 

Thank you for make it notice, i'm going to check it on the lab and inform about it, but as states before, the ASCLIN SPI mode features do not intent to be a full SPI as the QSPI, so maybe this is the way it meant to work.

Regards! :1

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David_R
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Hi @beamk 

According to the user manual part 2, the feature list for the ASCLIN:

page 1605, section 36.1

 

 

ASCLIN SPI Features
 SPI master modes (slave mode not supported):
– Four-wire or three-wire (with / without slave select output signal)
Up to 16-bit data width
Full-duplex and half-duplex
– Min. baud rate fA/ 268 435 456 MBaud (= 0.37 Baud @ 100 MHz fA module clock)
– Max. baud rate fA/ 4 MBaud (= 25 MBaud @ 100 MHz fA module clock)
Programmable leading and trailing delays

 

 

So it does not specified that it can be modify, the only register that can be change to modify the spi mode is:

page 1661, section 36.4.1

David_R_0-1706036249668.png

Whereas the feature list for the QSPI:

page 1795, section 37.1

 

 

Feature List for QSPI module.
 Master and Slave Mode operation
– Full-duplex operation
– Half-duplex operation
– Automatic slave select control
– Four-wire and three-wire type of connection
 Flexible data format
– Programmable number of data bits: 2 to 32 data bits (plus parity: 3 to 33 bits)
– Programmable shift direction: LSB or MSB shift first
– Programmable clock polarity: Idle low or idle high state for the shift clock
– Programmable clock phase: data shift with leading or trailing edge of the shift clock

 

 

 In this case the register ECONz controls the SPI operational mode,

page 1783

David_R_1-1706036616143.png

So if it's possible i'd recommend you to change to qspi, if this is not possible then the only solution that i can think of is generating the signals by software.

Cheers! :1

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beamk
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Thank you, David_R for the comprehensive info.

Sadly the same conclusion I had as well and all the QSPI slots are already taken.

 

I have to do a correction for my first post:

The default mode would be SPI mode 1 (MOSI changing with rising clock edge) and by changing the clock polarity it is possible to go to SPI mode 3 (MOSI changing with falling clock edge). At least most devices can be covered this way.

Of course it would be nice to be able to go to mode 0 and mode 2 as well.

Best Regards

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David_R
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Hi @beamk 

As the clock phase can't be change (CPHA = 0),  the only modes of operation for ASCLIN SPI in theory will be 0 and 2

David_R_0-1706112857518.png

To confirm it, lets use this training example

BTW i just modify the output to make it more readable instead of ascii chars,

 

uint8 g_spiTxBuffer[] = {'E', 'T'}; <-- Original
uint8 g_spiTxBuffer[] = { 0xDA, 0xED}; <-- Modified

 

Here's the logic analyzer settings:

David_R_5-1706114187555.png

Mode 0,  

David_R_1-1706113193933.png

Mode 1:

David_R_2-1706113302843.png

Mode 2:

David_R_3-1706113397296.png

Mode 3:

David_R_4-1706113468907.png

So it seems that it could be use it as normal SPI, unless the slave uses mode 2, but as far as can tell almost all new SPI chips sensors, memories, ...,  supports at least two modes of operation, have you tried to connect with the salve?, if don't, please do it and let me know if it worked.

One last test to see if it works with more data

David_R_0-1706114771204.png

Yep, the same output as before, so it looks like it works, from time to time a byte is corrupted but it could be because the analyzer so i'd recommend to add a CRC just to have peace of mind.

Cheers! :1

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beamk
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Hello David_R,

thank you for your detailed reply! From what I understood SPI mode 0 would change the MOSI (shift out) on the falling edge of the clock. (Serial Peripheral Interface – Wikipedia)

This would mean that your first plot shows an SPI mode 1 connection?

What I saw on my oscilloscope plots was also a change in MOSI with the rising clock edge (SPI mode 1)
or when changing the parameter CPOL to 1 with the falling clock edge (SPI mode 3).

The device I've communicated with reacted without errors to the CPOL=1 connection and is meant by its datasheet to be used with either SPI mode 0 or SPI mode 3. So this lines up. (CPOL=0 did not work properly)

Best Regards
beamk

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David_R
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Hello @beamk 

That's correct, for mode 0 the data sampled on rising edge and shifted out on the falling edge, the first plot is corresponding to a SPI mode 0 transfer, due the logic analyzer maybe it can't be noticed the details, but the settings were set to decode this mode.

Let me do it again using an oscilloscope to confirm it, but with you results we can conclude that the ASCLIN SPI works with mode 1 and 3 which makes sense to try to cover the most sensors, 

Thank you for make it notice, i'm going to check it on the lab and inform about it, but as states before, the ASCLIN SPI mode features do not intent to be a full SPI as the QSPI, so maybe this is the way it meant to work.

Regards! :1

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