- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, could anyone advice how to trigger ALM9[15] Short to Low/High Alarm by editing some registers?
Solved! Go to Solution.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The CPU alarm reaction is in SMU_AG9CF0.CF15, SMU_AG9CF1.CF15, and SMU_AG9CF2.CF15 - what's in those registers? For example, to have ALM9[15] cause an NMI, you'd configure AGiCFj per Table 528 on page 1302 of AURIXTC3XX_um_part1_v2.0.pdf:
SMU_NMI = 5 = 101b
SMU_AG9CF0.CF15 = 1
SMU_AG9CF1.CF15 = 0
SMU_AG9CF2.CF15 = 1
Also make sure SCU_TRAPDIS0.CPU0SMUT=0 (the default is 1=trap disabled). Possibly other CPUxSMUT and SCU_TRAPDIS1.CPUxSMUT, depending on how many CPUs you want to receive the trap.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ivnn. Our experts warned me not to try doing that 😉
When customers want to verify their SMU configuration, my advice is usually to stay away from the fault injection path, because:
1) Some of those are extraordinarily difficult!
2) Some safety mechanisms have no fault injection mechanism, because Infineon didn't want to add the risk of accidental activation of a fault injection mechanism.
Another way of verifying the SMU configuration is to leave the SMU in START state, and then you can simply write to the alarm registers (e.g., SMU_ALM4):
In the START state software has the possibility to “emulate” the occurrence of input alarm events by writing at an
AG<x> address.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
hi🤘, thanks for the quick answer!
could you pls hint the right address name to write for example for ALM9[15]
and do we need to unlock something before write?
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi ivnn. When the SMU is in start state (SMU_DBG.SSM=0), you can write to SMU_AG0...SMU_AG11. You can see that SMU_AGi registers are Safety Endinit protected in Table 537 - Register Overview - SMU on page 1324 of AURIXTC3XX_um_part1_v2.0.pdf.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi, the idea was add a breakpoint in trap_handler and after ALx editing reach it
Steps:
in state SMU_DBG.SSM=0
disable ENDINIT by CBS_OCNTRL 0x000000C0
and after the modification for example SMU_AG10 bit SF16 to 0x01 press RUN and nothing happened
Expectation was it'll stop on breakpoint but its keeps in RUN
Any ideas? maybe something else should be configured ?
Thanks
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The CPU alarm reaction is in SMU_AG9CF0.CF15, SMU_AG9CF1.CF15, and SMU_AG9CF2.CF15 - what's in those registers? For example, to have ALM9[15] cause an NMI, you'd configure AGiCFj per Table 528 on page 1302 of AURIXTC3XX_um_part1_v2.0.pdf:
SMU_NMI = 5 = 101b
SMU_AG9CF0.CF15 = 1
SMU_AG9CF1.CF15 = 0
SMU_AG9CF2.CF15 = 1
Also make sure SCU_TRAPDIS0.CPU0SMUT=0 (the default is 1=trap disabled). Possibly other CPUxSMUT and SCU_TRAPDIS1.CPUxSMUT, depending on how many CPUs you want to receive the trap.