将TC397的QSPI模块的CPOL设置为1

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xuxu
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将TC397的QSPI模块的CPOL设置为1,但是示波器显示时钟引脚输出信号的空闲状态并不是高电平,请问是为什么?在debug状态发现其CPOL寄存器确实是 1

IMG_20230419_175256.jpg

mmexport1681899739540.jpg

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1 解答
Jeremy_Z
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Hi @xuxu ,

After digging deeper, I find that you can set the phase period of idle A and idle B to make the SCLK level become high, for instance, set config->mode.csInactiveDelay = SpiIf_SlsoTiming_2, besides setting config->mode.clockPolarity = SpiIf_ClockPolarity_idleHigh.
And the SPI wave will be illustrated below.

2023-04-24_15h40_43.png

BR,

Jeremy

在原帖中查看解决方案

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psyp_wang
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我只看过datasheet,cpol 默认应该是0,就是idle状态下sck为低电平,cpol

是在ECON扩展寄存器中配置的,是不是配错通道了?

xuxu
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hi,@psyp_wang

确认了一下通道,没有选错

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Jeremy_Z
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Dear @xuxu ,

请使用例程看看能否复现问题,例程默认是ilde状态下,clock引脚为低电平,你需要修改。

 

void SpiIf_initChannelConfig(SpiIf_ChConfig *config, SpiIf *driver)
{
    config->driver               = driver;
    config->baudrate             = 0;
    config->mode.enabled         = 1;
    config->mode.autoCS          = 1;
    config->mode.loopback        = 0;
    config->mode.clockPolarity   = SpiIf_ClockPolarity_idleLow;
    config->mode.shiftClock      = SpiIf_ShiftClock_shiftTransmitDataOnLeadingEdge;
    config->mode.dataHeading     = SpiIf_DataHeading_msbFirst;
    config->mode.dataWidth       = 8;
    config->mode.csActiveLevel   = Ifx_ActiveState_low;
    config->mode.csLeadDelay     = SpiIf_SlsoTiming_0;
    config->mode.csTrailDelay    = SpiIf_SlsoTiming_0;
    config->mode.csInactiveDelay = SpiIf_SlsoTiming_0;
    config->mode.parityCheck     = 0;
    config->mode.parityMode      = Ifx_ParityMode_even;
    config->errorChecks.baudrate = 0;
    config->errorChecks.phase    = 0;
    config->errorChecks.receive  = 0;
    config->errorChecks.transmit = 0;
}

 

BR,

Jeremy

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xuxu
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hi,@Jeremy_Zhou

我就是在例程的基础上修改的,未修改时

IMG_20230419_175343.jpg

当cpol=0时是正常的,当我修改为1就变成了 我上文那个不正常的图了

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xuxu
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hi @Jeremy_Z 

在你提供的例程下,修改CPOL=1,出现的现象仍然是

xuxu_0-1682238504931.png

请问还有什么别的方法可以尝试吗?

 

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psyp_wang
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请问你的QSPI是配置为了主机还是从机 如果是从机的话 cpol是被固定为0的

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xuxu
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我是使用板载的两个QSPI模块进行测试,我是更改了主机的时钟配置

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psyp_wang
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好吧,我也没用过,作为一只小菜鸟,我正好最近在看datasheet做调研,标准协议CPOL=0,那么SCK在idle的时候是低电平,CPOL=1,idle状态为高电平,可我看你的波形前面是低的 后面是高的,不知道状态机跳转有没有问题

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xuxu
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请问状态机跳转问题指的是我在寄存器设置为1,但最后实际为0了的意思么?

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psyp_wang
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可能我说的不对啊,我只是猜测:英飞凌的QSPI传输数据的状态机的IDLE状态分 IDLE A-IDLEB, cpha和cpol的配置是在这个状态“吃”进来的,你可以试下把 idle delay length调一下

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xuxu
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你说得对!感谢!

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psyp_wang
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hi xuxu,关于cpol的问题,请教一下 你是调了哪个参数?我看文档 idle delay length这个参数 默认值是最大8个unit

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xuxu
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hi psyp_wang

我调整了csInactiveDelay这个参数,如楼下  的示例。

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xuxu
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谢谢!解决了!时钟正常了,我一开始提出这个问题是因为从机发送的数据和主机接收的数据不同,我还以为是时钟造成的。现在时钟正常了,数据仍然不对,您有什么见解吗?

 

如下图所示,红色曲线。我设置cph和cpol都是1,此时应该像蓝色曲线一样上升沿采集,但是红色曲线并不

IMG_20230424_173329.jpg

符合

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psyp_wang
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 不好意思 没太明白红线和蓝线分别代表什么

数据的波形是不是对的?是否考虑过时序的问题?

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psyp_wang
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还有 cpha=1 是下降沿采样,你用板子两个QSPI互相通信,应该要考虑timing的问题英飞凌的QSPI的采样点 应该是可配的,就是ABC这三个配置波特率的参数 调整下采样点试试

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xuxu
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红色是从机发送的数据,蓝色是主机发送的数据

好的!谢谢!我尝试一下

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Jeremy_Z
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Hi @xuxu ,

除了更改CPOL位外,还有修改其它地方吗?

BR,

Jeremy

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xuxu
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hi @Jeremy_Z 

其余地方都未更改,就是官方例程

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Jeremy_Z
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Hi @xuxu ,

After digging deeper, I find that you can set the phase period of idle A and idle B to make the SCLK level become high, for instance, set config->mode.csInactiveDelay = SpiIf_SlsoTiming_2, besides setting config->mode.clockPolarity = SpiIf_ClockPolarity_idleHigh.
And the SPI wave will be illustrated below.

2023-04-24_15h40_43.png

BR,

Jeremy

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xuxu
Level 3
Level 3
25 sign-ins 25 replies posted 5 questions asked

谢谢!解决了!时钟正常了,我一开始提出这个问题是因为从机发送的数据和主机接收的数据不同,我还以为是时钟造成的。现在时钟正常了,数据仍然不对,您有什么见解吗?

如下图所示,红色曲线。我设置cph和cpol都是1,此时应该像蓝色曲线一样上升沿采集,但是红色曲线并不符合

IMG_20230424_173329.jpg

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Jeremy_Z
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Hi @xuxu ,

我觉得你最好检查一下,Slave device 支持的SPI总线模式是否与Master device相匹配。

BR,

Jeremy

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