I have never worked with multicore microcontrollers and I am trying to figure out how AURIX TC375 is working (it has 3 cores). I am using Multicore_1 example for KIT_AURIX_TC375_LK (presentation, github) and AURIX Development Studio. Basically, this example is using Core2 to toggle global variable, Core1 to turn off LED if this global var is FALSE and Core0 to turn on LED if global var is TRUE. Example imports and compiles nicely, but I have few questions.
- Memory usage from .map file looks like this
Why all instructions (code) are located in PFLASH? I have expected something to be put into PSPR (psram in .map) for each core. When PSPR will be used then?
- Still, I suppose, it could be correct to store all instructions in PLFASH, but how controller decides on which core to run which instruction? How can I see that in .map file? Or how can I see which core execute what?
- Furthermore, I have found document "AURIX™ MULTI-CORE TRICORE™ PROGRAMMING ESSENTIALS", where startup procedure is described as
But I could not find nothing like "main.c" "startup" or similar in example project. Is it somehow done automatically or hidden in AURIX Development Studio?
- Another document (TASKING VX-toolset for TriCore User Guide) mentions that
AURIX TC3xx derivatives support a Program Flash Memory per core (PFLASH0 .. PFLASHn). Where n is the number of cores minus 1. PFLASH memories are located in 3 MB pages. PFLASH core 0 starts at offset 0. For each next core its PFLASH offset is at the next 3 MB offset.
So I presumed, that .text.Cpu0_Main.core0_main .. .text.Cpu2_Main.core2_main would be located with this 3 MB offset, but according to .map file they are not:
Section | Space addr | Chip addr
.text.Cpu0_Main.core0_main | 0x80002218 | 0x00002218
.text.Cpu1_Main.core1_main | 0x803003ec | 0x000003ec
.text.Cpu2_Main.core2_main | 0x803005d0 | 0x000005d0
Offset between .core0_main and .core1_main is something like 3 MB (0x30000), but it is not true for offset between .core1_main and .core2_main. Why is that? Is there any other introductionary literature on this topic (AURIX startup code, multicore operation, PSPR/DSPR/PFLASH/LMU usage examples)?
2. By default, any core can access any instruction. For most applications, common libraries such as the operating system, MCAL, or iLLD are shared by all cores. There is no way to see what core executes what in the map file. The compiler generally doesn't know what core is executing each function.
3. The startup flow of an ADS project is:
- Configurations/Ifx_Cfg_SswBmhd.c: start address = 0xA0000000
LCF_STARTPTR_NC_CPU0 = 0xA0000000
"__START0" := LCF_STARTPTR_NC_CPU0;
start_address = _START
- Infra/Ssw/TC375/Tricore/Ifx_Ssw_Tc0.c, _START()
- Ifx_Ssw_Tc0.c, __StartUpSoftware() ... __StartUpSoftware_Phase5()
- Ifx_Ssw_Tc0.c, __StartUpSoftware_Phase6(): starts CPUs 1..5
- Ifx_Ssw_Tc0.c, __Core0_start()
- Cpu0_Main.c, core0_main
4. That TASKING document is a little misleading. "Program Flash Memory per core" refers to the fact that each PFLASH physical bank has a local CPU path that is faster than going over the SRI bus. But by default, any CPU core can access any instruction in any PFLASH bank. The default linker setup just allocates functions into all of PFLASH.
this made things clearer,
i still have a question, in ARM based architectures, when i used to do a jump from bootloader to application.
we used to jump to reset handlers which is located in 2n location of the applicatio.hex...
in aurix based, where should i jump to ,to start running my application?