CYW43455 LPO_IN

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maticee
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Hi there,
We are using the CYW43455 and were wondering if there was a sequencing requirement for when the LPO_IN must be active. Can it come up at any time? Can it come up with VBATT? With VIO?

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Murali_R
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We recommend using an external LPO in designs instead of using the internal LPO.

For the sequencing, the startup signalling sequence prior to software download is available at figure 7 of page 22 of the datasheet.

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Murali_R
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We recommend using an external LPO in designs instead of using the internal LPO.

For the sequencing, the startup signalling sequence prior to software download is available at figure 7 of page 22 of the datasheet.

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maticee
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Thank you for the response.

Is it okay for the LPO_IN to come up after VBATT and VIO?

Also,  does the voltage of LPO_IN matter? Does it have to be referenced to VBATT or VIO?

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Murali_R
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Whatever timing diagram I mentioned in my previous response assumes that the VBAT is already present. So yes, it's fine.

Yes, the input signal amplitude should be 0.2 to 3.3v Vpp. Details available in Table 4, page 15 of the datasheet.

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maticee
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Great. To confirm, our VBATT is 3.3V and VIO is 1.8V.

Based on your response, it does not matter the high voltage of the LPO. We can tie it directly to a 3V3 or 1V8 oscillator

Based on your response, LPO can come up at any time during operation. Before or after VBATT and VIO.

Please confirm the above two statements.

 

Other questions from our integration team:

What are the following signals referenced to? What is the VIH of the pins?

LPO_IN
BT_REG_ON
WL_REG_ON

 

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Any updates?

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Murali_R
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I did not mention that you should tie to an the oscillator o/p for the voltage. The input voltage should be in that range. But I think it should be fine. But check  If you see there's an issue with the power/current umbers you need if you source it from the oscillator. 

Also, i mentioned that VBAT/VIO would be present before the clock starts/sets in.

LPO_IN -> ext clk input

BT_REG_ON -> BT control pin

WL_REG_ON -> WIFI control pin

VIH would be 0.65*VDDIO if 1.8V is the inp and 2v if the VDDIO is 3v

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Hi there, I am unfortunately not following and there seems to be mixed information coming from this thread.

I will attempt to ask questions in a clearer fashion.

Our application uses VBATT of 3.3V and VIO of 1.8V

1. Confirm: WL_REG_ON and BT_REG_ON reference VIO. VIH is 0.65*1.8V

2. What is the VIH of LPO_IN?

3. What are the sequencing restrictions on LPO_IN/? Can it come up either before or after VBATT?
figure 7 of page 22 is not clear and shows that LPO_IN is already active when vbatt comes up

 

Please address these so we can make sure our design works as expected the first time.

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Murali_R
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1. Yes

2. LPO_IN is ultimately a digital Input pin as far as I know. So the previous limit holds here.

3. LPO_IN should come after VBAT. "Timing diagram assumes VBAT is present."

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maticee
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Thank you for confirming.

1/2: Can I find this information anywhere on the datasheet. Regarding WL_REG_ON and BT_REG_ON, nowhere in the datasheet is VIH and VIL mentioned.  Table 24 mentions that it is not associated with any power rail. Can we have the specifications for the PMU in this case?

For LPO_IN, our concern is that table 4 does not mention a VIH or VIL - it says 200–3300 mvpp which is different from what you said. It seems to be independent of the VIO voltage

3. Looking at figure 41, the oscillator comes up before VBATT which is also different from what you are saying.

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Murali_R
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Regarding the VIH info, table 28 specifies this for digital pins. WL_REG_ON and BT_REG_ON operate at either 1 or 0 which essentially makes them a digital pin.

200-3300mV is the operating range input that you need to feed to external oscillator for it to work with the chip.

In figure 7, the line at the end says the VBAT is already present for the startup sequence. But the figure 41 seems to indicate after. Not sure if this effects the boot up since WL_REG_ON as well as BT_REG_ON comes 2 sleep cycles after. Will confirm this internally to be sure and clarify.

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Murali_R
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Figure 7 is on timing sequence requirement for BT FW download, their key signals are bt_reg_on, bt_uart_cts, bt_uart_rts. it assumes the chip is power-up ready, Vbat is present. Even chip is power-up ready and Vbat is present, to download BT FW, the timing sequence between those signals should be taken care.

Figure 41 is to show the power-up timing requirement between Vbat, VDDIO, xx_reg_on. To power up 43455 chip successfully, the host hardware platform must follow that power-up sequence and timing requirement defined in section 19. With successful power-up, the host platform just could downlaod wifi FW and BT FW to bring up wifi and BT functons.

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Hi there, please confirm below

1. WL_REG_ON and BT_REG_ON reference VIO

2. Oscillator voltage output is not referenced to VIO. Both 1.8V or 3.3V oscillators are okay to use independent of VIO

3. We still do not have a clear answer regarding this. What are the restrictions with LPO_IN coming up. I am happy to take this offline but our team has not yet been able to get a point blank answer to this problem.

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Murali_R
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1. yes

2. yes

3. Follow figure 41

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maticee
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As mentioned, figure 41 is not clear on whether it comes up before / after.

Based on that figure, I would assume it does not matter as it is not clear by any means.

Please specify and give a final answer on before, after, or does not matter.

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Murali_R
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MuraliR_36_0-1648528279754.png

I hope this makes it clear that Vbat comes up after the clock.

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Thank you for the clear response. See final confirmations below

VBATT = 3.3V
VIO = 1.8V

1. WL_REG_ON and BT_REG_ON reference VIO - 1.8V

2. Oscillator voltage output is not referenced to VIO. Both 1.8V or 3.3V oscillators are okay to use independent of VIO - we will use 3.3V

3. LPO_IN must come up before or at the same time as VBAT - these will be connected to the same supply. Please confirm that is okay

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