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AIROC™ Wi-Fi and Wi-Fi Bluetooth Combos Forum Discussions

fvaussard
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Hello,

We are testing a CYW43439 to integrate it in our next product. We are using the gSPI mode and thus are pulling the strapping pin SDIO_DATA_2 low. But we noticed that there is a strong internal pull-up, since using a 10k pull-down will increase the power consumption by 160µA, which is not acceptable for us. As a result, we are connecting SDIO_DATA_2 to a GPIO to select the mode at boot. I have 2 questions regarding this:

  1. What is the minimum time that SDIO_DATA_2 should be held low after enabling WL_REG_ON ? The datasheet mentions "Sampling occurs a few milliseconds after an internal POR", but internal POR seems to come (1.5 + 3)ms after WL_REG_ON if I read "Figure 15. WLAN Boot-Up Sequence" correctly. Is that correct ?
  2. Can we disable the internal pull-up on SDIO_DATA_2 by writing some register ? This could simplify our schematics.

As a final note, a pull-down of 10k on SDIO_DATA_2 was not enough to select gSPI contrary to what is written in the datasheet. I had to use a 1kΩ, which increases even more the power consumption. I did not tested all the intermediate values though.

Best regards,

Floroian

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MuraliR_36
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Is this a module based design? If so, have you checked with your module vendor?

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MuraliR_36
Moderator
Moderator
Moderator
250 sign-ins 250 replies posted 100 solutions authored

Is this a module based design? If so, have you checked with your module vendor?

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