We have a custom PCBA similar to the CYW943907AEVAL1F. Trying to load firmware via the JTAG port, we receive a Could not establish a connection failure. The same JTAG running the same software does successfully connect to the Evaluation Module. Attaching log files from both attempts to connect via JTAG.
JFLASH V7x Boot on custom PCBA:
Connecting ...
- Connecting via USB to probe/ programmer device 0
- Probe/ Programmer firmware: J-Link V10 compiled Sep 24 2021 16:39:44
- Device "CYW43907" selected.
- Target interface speed: 4000 kHz (Fixed)
- VTarget = 3.238V
- Found SW-DP with ID 0x5BA02477
- DPIDR: 0x5BA02477
- Scanning AP map to find all available APs
- AP[2]: Stopped AP scan as end of AP map has been reached
- AP[0]: APB-AP (IDR: 0x44770002)
- AP[1]: JTAG-AP (IDR: 0x24760010)
- Iterating through AP map to find APB-AP to use
- AP[0]: APB-AP found
- ROMTbl[0][0]: CompAddr: 80001000 CID: B105900D, PID: 008BBC14 Cortex-R4
- Found Cortex-R4 r1p4
- 4 code breakpoints, 4 data breakpoints
- Debug architecture ARMv7.0
- Found SW-DP with ID 0x5BA02477
- DAP error while determining CoreSight SoC version
- ERROR: Cortex-A/R (connect): Failed to temporarily halting CPU for reading CP15 registers.
- ERROR: Failed to connect.
Could not establish a connection to target.
Boot on the Evaluation Board is identical until reaching Debug architecture ARMv7.0:
- Debug architecture ARMv7.0
- Data endian: little
- Main ID register: 0x411FC144
- I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
- D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
- TCM Type register: 0x00010001
- MPU Type register: 0x00000800
- System control register:
- Instruction endian: little
- Level-1 instruction cache enabled
- Level-1 data cache enabled
- MPU enabled
- Branch prediction enabled
- Executing init sequence ...
- Initialized successfully
- Target interface speed: 4000 kHz (Fixed)
- Found 1 JTAG device. Core ID: 0x5BA02477 (None)
- Connected successfully
