Generate an 8.192 MHz clock signal on the CYW20706EVAL board for I2S Master Clock signal for Digilent Pmod I2S2 audio codec

[markandreck-01]

Hi,

I want to generate an 8.192 MHz clock signal on the CYW20706EVAL board for my I2S audio codec (Digilent Pmod I2S2)

I want to perform bidirectional audio communication between the CYW20706EVAL(configured as an Audio gateway) and a Bluetooth headset. I successfully managed to get the two devices connected together.

I understand that in the Audio gateway configuration, the audio is automatically routed to the PCM/I2S pins of the CYW20706EVAL. I checked the pins using an oscilloscope, the SDOut pin shows that there is data present whenever I speak into the mic on the headset side, WS/LRCK/PCM_SYNC pin shows a freq = 16 kHz (cause I'm using Wideband Speech), BCK/PCM_CLK pin shows a freq = 512 kHz, however, in addition  to these signals my audio codec (Digilent Pmod I2S2) requires a Master Clock of 8.192 MHz that corresponds with the Bit clock (BCK).

I tested it by providing an external clock signal of 8.192 MHz from an external source and the bidirectional audio communication worked perfectly.

I've identified two possible methods to generate the required master clock signal (8.192 MHz) from the CYW20706EVAL, which are PWM or Auxiliary clock and I've come across certain problems with each method.

PWM problem - I can only generate signals up to 5 MHz and above 10 MHz and nothing in between

ACLK problem - I'm unable to get any clock output signal on any of the GPIO pins P32, P36 and P33, P37 for ACLK0 and ACLK1 clocks respectively. This is despite following the instructions in the ACLK documentation given here https://infineon.github.io/btsdk-docs/BT-SDK/20719-B2_Bluetooth/API/group___aux_clk_driver.html , to first configure the desired GPIO pin for output for aclk. And also referring to the HW User Guide.

I've pasted my code for the Auxiliary clock (ACLK) configuration below as well;

wiced_hal_gpio_configure_pin(WICED_P32, GPIO_OUTPUT_ENABLE, GPIO_PIN_OUTPUT_HIGH);
wiced_hal_aclk_enable(8192000, ACLK0, ACLK_FREQ_24_MHZ);

1. Please let me know if there is something that I need to implement, that I could be missing out on any of the two methods.

2. Please suggest any other methods that I could use to generate an 8.192 MHz clock on the CYW20706EVAL GPIO pins.

I'm looking forward to hearing from you.

Regards

Mark

[Tushar_b · Accepted solution]

We would recommend using the external clock for generating 8.192MHz. Since, it is not  possible to generate the accurate requested clock frequency using CYW20706.

If you want to try using ACLK can you try the below code.

#define REG32(ADDR) *((volatile UINT32*)(ADDR))
#define iocfg_p33_adr 0x00336284

wiced_hal_gpio_configure_pin(33,GPIO_OUTPUT_ENABLE|GPIO_PULL_UP,GPIO_PIN_OUTPUT_HIGH);
REG32(iocfg_p33_adr)=0x0010;
wiced_hal_aclk_enable(1000*1000, ACLK1, ACLK_FREQ_24_MHZ);

Regards,

Tushar

[markandreck-01]

Hi Tushar,

Thanks for the response. I have tried to implement your suggested code and I managed to generate a clock on GPIO pin 33 from ACLK 1, however the generated clock wasn't the desired one. It seems like I will just have to settle for an external clock.