CYW920706WCDEVAL HCI UART RX FIFO hardware buffer size?

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YR1
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What is HCI UART RX FIFO  hardware buffer size in CYW920706WCDEVAL ?

I can't find it in CYW920706WCDEVAL-Hardware-User-Guide.pdf.

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DheerajPK_41
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Ok. Kindly check the datasheet.

1.6.2 HCI UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 4Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYW20706 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 k baud........

https://www.infineon.com/dgdl/Infineon-CYW20706_Bluetooth_SoC_for_Embedded_Wireless_Devices-DataShee...

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DheerajPK_41
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Hi,

Please check the comments in wiced_transport.h

Maximum size of the buffer that can be allocated is 264 bytes. Creates a buffer pool for transport usage. The application shall create the buffer pool if it has to send packet of size > 264 bytes.

Thanks,

-Dheeraj.P.K

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Sorry.

    I mean the FIFO  hardware buffer size.  Not the buffer pool in application layer.

    Similar like.

      9.4 Peripheral UART

         The RX and TX FIFO hardware buffer size is 256 bytes.

 

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DheerajPK_41
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Ok. Kindly check the datasheet.

1.6.2 HCI UART Interface
The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 4Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYW20706 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 k baud........

https://www.infineon.com/dgdl/Infineon-CYW20706_Bluetooth_SoC_for_Embedded_Wireless_Devices-DataShee...

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Thank you.

   I want to use the HCI UART RAW mode. 

   I want to confirm that the RX flow control works.

   I use the sample code in the attachment.

   When the RX data callback , I return 0. I want the application RX buffer full. Then it will lead to the RX FIFO hardware buffer full. I guess it will trigger the RX flow control. The RTS will be high?

   My test is that. I sent about 9K data. But the RTS is still low. It seems that the flow control doesn't work.

Is my test or my assumption right?

Can you reproduce it? 

 

 

 

  

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DheerajPK_41
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Update:

For HCI Raw UART mode application, please refer the below application.

https://github.com/Infineon/mtb-example-btsdk-hal-uart-raw-mode

 

As per the spec, the hardware FIFO is as below. So in order to break it, the Host should send a bigger packet than the hardware buffer. Then the RTS will get De-asserted and further data transfer will get blocked.

"The CYW20706 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates"

Thanks,

-Dheeraj.P.K

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