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AIROC™ Bluetooth Forum Discussions

HTerm1
Employee
5 sign-ins First like given First reply posted
Employee

Is there a way to route a clock with 2MHz to e.g. P30 ? Following code snips did not work.

1)

wiced_hal_gpio_select_function(WICED_P30, WICED_ACLK_0); 

wiced_hal_aclk_enable(2000000, ACLK0, ACLK_FREQ_24_MHZ); 

 

2)

wiced_hal_gpio_configure_pin(WICED_P30, GPIO_OUTPUT_ENABLE, GPIO_PIN_OUTPUT_HIGH); 

wiced_hal_aclk_enable(2000000, ACLK0, ACLK_FREQ_24_MHZ);

 

3) 

first setting Aclk[0] to P30 with DeviceConfigurator

wiced_hal_aclk_enable(2000000, ACLK0, ACLK_FREQ_24_MHZ);

 

BR

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1 Solution
Owen_Zhang123
Moderator
Moderator 500 solutions authored 250 sign-ins 1000 replies posted
Moderator

The ACLK uses the external 24MHz crystal as the source clock. The accuracy depends on the external clock.

View solution in original post

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6 Replies
Owen_Zhang123
Moderator
Moderator 500 solutions authored 250 sign-ins 1000 replies posted
Moderator

Could you use the PWM output as a workaround?

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HTerm1
Employee
5 sign-ins First like given First reply posted
Employee

Thanks for your reply. Somehow option 3) is now working.

ScottK_91
Employee
10 sign-ins 5 sign-ins First comment on KBA
Employee

Hello,  when a GPIO is configured as an ACLK and is set at 24 MHZ output, what are the clock characteristics (PPM, jitter, phase noise, DC characteristics) to determine if this is a suitable clock for an audio DSP?

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Owen_Zhang123
Moderator
Moderator 500 solutions authored 250 sign-ins 1000 replies posted
Moderator

The ACLK uses the external 24MHz crystal as the source clock. The accuracy depends on the external clock.

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ScottK_91
Employee
10 sign-ins 5 sign-ins First comment on KBA
Employee

Thanks.  Is the ACLK passed as a reference at 24 MHz out of a GPIO pin (essentially a divider bypass) or only used as a base clock generating a divided signal?

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Owen_Zhang123
Moderator
Moderator 500 solutions authored 250 sign-ins 1000 replies posted
Moderator

It is only used as a base clock generating a divided signal.

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