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TRAVEO™ T2G MCU: SRAMの電源管理におけるアドレス範囲

TRAVEO™ T2G MCU: SRAMの電源管理におけるアドレス範囲

Matsuzawa
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Original Translation: TRAVEO™ T2G MCU: SRAM address ranges for power management

TRAVEO™ T2GのSRAMはスタンバイモード時の消費電流の低減のために、ユニット毎に電源の管理が可能です。特にユニット SRAM0は32KB単位で個別に制御が出来ます。

以下に製品毎のレジスタと対応するアドレスを示します。

T2G Body Entry series

SRAM#

Register

Address

CYT2B6

CYT2B7

CYT2B9

CYT2BL

SRAM0

CPUSS_RAM0_PWR_MACRO_CTL0

0x08000000 to 0x08007FFF

CPUSS_RAM0_PWR_MACRO_CTL1

0x08008000 to 0x0800FFFF

CPUSS_RAM0_PWR_MACRO_CTL2

-

-

0x08010000 to 0x08017FFF

CPUSS_RAM0_PWR_MACRO_CTL3

-

-

0x08018000 to 0x0801FFFF

CPUSS_RAM0_PWR_MACRO_CTL4

-

-

-

0x08020000 to 0x08027FFF

CPUSS_RAM0_PWR_MACRO_CTL5

-

-

-

0x08028000 to 0x0802FFFF

CPUSS_RAM0_PWR_MACRO_CTL6

-

-

-

0x08030000 to 0x08037FFF

CPUSS_RAM0_PWR_MACRO_CTL7

-

-

-

0x08038000 to 0x0803FFFF

SRAM1

CPUSS_RAM1_PWR_CTL

-

0x08010000 to 0x0801FFFF

0x08020000 to 0x0803FFFF

0x08040000 to 0x0807FFFF

 

T2G Body High series

SRAM#

Register

Address

CYT3BB/4BB

CYT4BF

SRAM0

CPUSS_RAM0_PWR_MACRO_CTL0

0x28000000 to 0x28007FFF

CPUSS_RAM0_PWR_MACRO_CTL1

0x28008000 to 0x2800FFFF

CPUSS_RAM0_PWR_MACRO_CTL2

0x28010000 to 0x28017FFF

CPUSS_RAM0_PWR_MACRO_CTL3

0x28018000 to 0x2801FFFF

CPUSS_RAM0_PWR_MACRO_CTL4

0x28020000 to 0x28027FFF

CPUSS_RAM0_PWR_MACRO_CTL5

0x28028000 to 0x2802FFFF

CPUSS_RAM0_PWR_MACRO_CTL6

0x28030000 to 0x28037FFF

CPUSS_RAM0_PWR_MACRO_CTL7

0x28038000 to 0x2803FFFF

CPUSS_RAM0_PWR_MACRO_CTL8

0x28040000 to 0x28047FFF

CPUSS_RAM0_PWR_MACRO_CTL9

0x28048000 to 0x2804FFFF

CPUSS_RAM0_PWR_MACRO_CTL10

0x28050000 to 0x28057FFF

CPUSS_RAM0_PWR_MACRO_CTL11

0x28058000 to 0x2805FFFF

CPUSS_RAM0_PWR_MACRO_CTL12

0x28060000 to 0x28067FFF

CPUSS_RAM0_PWR_MACRO_CTL13

0x28068000 to 0x2806FFFF

CPUSS_RAM0_PWR_MACRO_CTL14

0x28070000 to 0x28077FFF

CPUSS_RAM0_PWR_MACRO_CTL15

0x28078000 to 0x2807FFFF

SRAM1

CPUSS_RAM1_PWR_CTL

0x28080000 to 0x280BFFFF

SRAM2

CPUSS_RAM2_PWR_CTL

-

0x280C0000 to 0x280FFFFF

 

T2G Cluster series

SRAM#

Register

Address

CYT2CL

CYT3DL

CYT4DN

CYT4EN

SRAM0

CPUSS_RAM0_PWR_MACRO_CTL0

0x08000000 to 0x08007FFF

0x28000000 to 0x28007FFF

CPUSS_RAM0_PWR_MACRO_CTL1

0x08008000 to 0x0800FFFF

0x28008000 to 0x2800FFFF

CPUSS_RAM0_PWR_MACRO_CTL2

0x08010000 to 0x08017FFF

0x28010000 to 0x28017FFF

CPUSS_RAM0_PWR_MACRO_CTL3

0x08018000 to 0x0801FFFF

0x28018000 to 0x2801FFFF

CPUSS_RAM0_PWR_MACRO_CTL4

0x08020000 to 0x08027FFF

-

0x28020000 to 0x28027FFF

CPUSS_RAM0_PWR_MACRO_CTL5

0x08028000 to 0x0802FFFF

-

0x28028000 to 0x2802FFFF

CPUSS_RAM0_PWR_MACRO_CTL6

0x08030000 to 0x08037FFF

-

0x28030000 to 0x28037FFF

CPUSS_RAM0_PWR_MACRO_CTL7

0x08038000 to 0x0803FFFF

-

0x28038000 to 0x2803FFFF

SRAM1

CPUSS_RAM1_PWR_CTL

0x08040000 to 0x0807FFFF

0x28020000 to 0x2803FFFF

0x28040000 to 0x2807FFFF

SRAM2

CPUSS_RAM2_PWR_CTL

-

0x28040000 to 0x2805FFFF

0x28080000 to 0x2809FFFF

 

More information

More like this (optional)

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Note:

このKBAは次のTRAVEO™ T2G MCUsに適用されます。

  • TRAVEO™ T2G CYT2xx series
  • TRAVEO™ T2G CYT3xx series
  • TRAVEO™ T2G CYT4xx series
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