Static Timing Analysis

Project : SCB_SpiCommMaster01
Build Time : 12/22/22 11:03:27
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
SPIS_IntClock CyHFCLK 2.000 MHz 2.000 MHz 66.388 MHz
SPIM_SCBCLK CyHFCLK 8.000 MHz 8.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
SPIM_SCBCLK(FFB) SPIM_SCBCLK(FFB) 8.000 MHz 8.000 MHz N/A
sclk_s(0)_PAD sclk_s(0)_PAD UNKNOWN UNKNOWN 33.926 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 66.388 MHz 15.063 484.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 1.480
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 4.504
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 77.622 MHz 12.883 487.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.480
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.324
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 79.214 MHz 12.624 487.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.295
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 86.520 MHz 11.558 488.442
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.480
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.904
macrocell4 U(0,0) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 2.254
statusicell2 U(1,0) 1 \SPIS:BSPIS:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 90.670 MHz 11.029 488.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.480
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.324
macrocell3 U(1,1) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.305
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 92.851 MHz 10.770 489.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.295
macrocell3 U(1,1) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.305
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 93.809 MHz 10.660 489.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.236
macrocell4 U(0,0) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 2.254
statusicell2 U(1,0) 1 \SPIS:BSPIS:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 126.678 MHz 7.894 492.106
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.480
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.904
macrocell11 U(0,0) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ SETUP 3.510
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 136.724 MHz 7.314 492.686
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.480
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.324
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 67.852 MHz 14.738
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,1) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_5 2.863
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_5 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Skew 1.398
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 68.320 MHz 14.637
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 2.110
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 3.550
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 68.343 MHz 14.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 2.110
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.545
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 69.580 MHz 14.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 2.110
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 3.285
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 69.672 MHz 14.353
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 2.110
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 3.266
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 2.271
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 56.158 MHz 17.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 2.110
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 3.550
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.170
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 56.173 MHz 17.802
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 2.110
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.545
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.170
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 57.006 MHz 17.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 2.110
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 3.285
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.170
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 57.068 MHz 17.523
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 2.110
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 3.266
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.170
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 60.875 MHz 16.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 2.110
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_2 2.819
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 60.875 MHz 16.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 2.110
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_3 2.819
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 61.931 MHz 16.147
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 2.110
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_4 2.539
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Skew 2.271
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 61.954 MHz 16.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 2.110
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_1 2.533
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Skew 2.271
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.000
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.324
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.000
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.904
macrocell11 U(0,0) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 5.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.000
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.324
macrocell3 U(1,1) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.305
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 6.508
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.000
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.904
macrocell4 U(0,0) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 2.254
statusicell2 U(1,0) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 7.090
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.236
macrocell4 U(0,0) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 2.254
statusicell2 U(1,0) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 7.200
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.295
macrocell3 U(1,1) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.305
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 7.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.000
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.324
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 9.054
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.295
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 10.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,1) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 0.000
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 4.504
macrocell7 U(1,1) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.159
statusicell1 U(1,1) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 5006.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,1) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_5 2.863
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_5 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -3.144
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5006.231
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.920
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 3.266
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5006.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.920
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 3.285
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5006.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.920
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.545
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5006.515
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.920
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 3.550
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -2.271
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 7.759
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.920
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_1 2.533
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 7.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.920
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_4 2.539
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 8.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.920
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_3 2.819
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 8.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.920
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_2 2.819
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.621
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.920
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 3.266
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.920
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 3.285
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.900
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.920
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.545
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.905
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.920
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 3.550
macrocell2 U(0,1) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.356
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -2.271
+ Input To Output Section
Source Destination Delay (ns)
ss_s(0)_PAD miso_s(0)_PAD 49.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
SCB_SpiCommMaster01 1 ss_s(0)_PAD ss_s(0)_PAD ss_s(0)_PAD 0.000
Route 1 ss_s(0)_PAD ss_s(0)_PAD ss_s(0)/pad_in 0.000
iocell5 P2[3] 1 ss_s(0) ss_s(0)/pad_in ss_s(0)/fb 15.357
Route 1 Net_273 ss_s(0)/fb Net_266/main_0 7.451
macrocell5 U(0,0) 1 Net_266 Net_266/main_0 Net_266/q 3.350
Route 1 Net_266 Net_266/q miso_s(0)/pin_input 6.073
iocell4 P2[1] 1 miso_s(0) miso_s(0)/pin_input miso_s(0)/pad_out 16.910
Route 1 miso_s(0)_PAD miso_s(0)/pad_out miso_s(0)_PAD 0.000
+ Input To Clock Section
+ sclk_s(0)_PAD
Source Destination Delay (ns)
ss_s(0)_PAD \SPIS:BSPIS:BitCounter\/enable 13.327
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 ss_s(0)_PAD ss_s(0)_PAD ss_s(0)/pad_in 0.000
iocell5 P2[3] 1 ss_s(0) ss_s(0)/pad_in ss_s(0)/fb 15.357
Route 1 Net_273 ss_s(0)/fb \SPIS:BSPIS:inv_ss\/main_0 6.564
macrocell1 U(1,0) 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/main_0 \SPIS:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/q \SPIS:BSPIS:BitCounter\/enable 2.573
count7cell U(0,0) 1 \SPIS:BSPIS:BitCounter\ SETUP 3.340
Clock Clock path delay -17.857
mosi_s(0)_PAD \SPIS:BSPIS:sR8:Dp:u0\/route_si 12.370
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 mosi_s(0)_PAD mosi_s(0)_PAD mosi_s(0)/pad_in 0.000
iocell3 P2[2] 1 mosi_s(0) mosi_s(0)/pad_in mosi_s(0)/fb 15.357
Route 1 Net_265 mosi_s(0)/fb \SPIS:BSPIS:mosi_to_dp\/main_0 5.643
macrocell9 U(0,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.227
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 3.650
Clock Clock path delay -17.857
mosi_s(0)_PAD \SPIS:BSPIS:mosi_tmp\/main_0 6.646
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 mosi_s(0)_PAD mosi_s(0)_PAD mosi_s(0)/pad_in 0.000
iocell3 P2[2] 1 mosi_s(0) mosi_s(0)/pad_in mosi_s(0)/fb 15.357
Route 1 Net_265 mosi_s(0)/fb \SPIS:BSPIS:mosi_tmp\/main_0 4.763
macrocell12 U(0,1) 1 \SPIS:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -16.984
+ Clock To Output Section
+ sclk_s(0)_PAD
Source Destination Delay (ns)
\SPIS:BSPIS:sR8:Dp:u0\/so_comb miso_s(0)_PAD 60.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \SPIS:BSPIS:sR8:Dp:u0\ \SPIS:BSPIS:sR8:Dp:u0\/clock \SPIS:BSPIS:sR8:Dp:u0\/so_comb 12.160
Route 1 \SPIS:BSPIS:miso_from_dp\ \SPIS:BSPIS:sR8:Dp:u0\/so_comb Net_266/main_1 2.267
macrocell5 U(0,0) 1 Net_266 Net_266/main_1 Net_266/q 3.350
Route 1 Net_266 Net_266/q miso_s(0)/pin_input 6.073
iocell4 P2[1] 1 miso_s(0) miso_s(0)/pin_input miso_s(0)/pad_out 16.910
Route 1 miso_s(0)_PAD miso_s(0)/pad_out miso_s(0)_PAD 0.000
Clock Clock path delay 20.128