Static Timing Analysis

Project : Design01
Build Time : 10/27/21 16:30:56
Device : CYBLE-214015-01
Temperature : -40C - 85C
VDDA : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_1_SampleClk(FFB) CapSense_1_SampleClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_1_SenseClk(FFB) CapSense_1_SenseClk(FFB) 188.235 kHz 188.235 kHz N/A
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFClk CyHFClk 48.000 MHz 48.000 MHz N/A
CapSense_1_SampleClk CyHFClk 188.235 kHz 188.235 kHz N/A
CapSense_1_SenseClk CyHFClk 188.235 kHz 188.235 kHz N/A
SPIM_1_IntClock CyHFClk 2.000 MHz 2.000 MHz 55.423 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFClk CyLFClk 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySysClk CySysClk 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:RxStsReg\/status_6 55.423 MHz 18.043 481.957
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 5.280
Route 1 \SPIM_1:BSPIM:rx_status_4\ \SPIM_1:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \SPIM_1:BSPIM:rx_status_6\/main_5 5.601
macrocell4 U(1,0) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_5 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.242
statusicell2 U(1,0) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:sR8:Dp:u0\/so_comb Net_57/main_4 70.761 MHz 14.132 485.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ \SPIM_1:BSPIM:sR8:Dp:u0\/clock \SPIM_1:BSPIM:sR8:Dp:u0\/so_comb 8.300
Route 1 \SPIM_1:BSPIM:mosi_from_dp\ \SPIM_1:BSPIM:sR8:Dp:u0\/so_comb Net_57/main_4 2.322
macrocell6 U(1,1) 1 Net_57 SETUP 3.510
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:TxStsReg\/status_3 74.008 MHz 13.512 486.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 2.110
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.118
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.364
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:TxStsReg\/status_3 75.775 MHz 13.197 486.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_0 2.110
Route 1 \SPIM_1:BSPIM:count_0\ \SPIM_1:BSPIM:BitCounter\/count_0 \SPIM_1:BSPIM:load_rx_data\/main_4 2.803
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_4 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.364
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:TxStsReg\/status_3 75.792 MHz 13.194 486.806
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_4 2.110
Route 1 \SPIM_1:BSPIM:count_4\ \SPIM_1:BSPIM:BitCounter\/count_4 \SPIM_1:BSPIM:load_rx_data\/main_0 2.800
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_0 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.364
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:TxStsReg\/status_3 75.832 MHz 13.187 486.813
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_3 2.110
Route 1 \SPIM_1:BSPIM:count_3\ \SPIM_1:BSPIM:BitCounter\/count_3 \SPIM_1:BSPIM:load_rx_data\/main_1 2.793
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_1 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.364
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:TxStsReg\/status_3 75.838 MHz 13.186 486.814
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:load_rx_data\/main_2 2.792
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_2 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:TxStsReg\/status_3 3.364
statusicell1 U(0,0) 1 \SPIM_1:BSPIM:TxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:RxStsReg\/status_6 76.046 MHz 13.150 486.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 2.110
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:rx_status_6\/main_3 3.878
macrocell4 U(1,0) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_3 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.242
statusicell2 U(1,0) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 76.453 MHz 13.080 486.920
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_1 2.110
Route 1 \SPIM_1:BSPIM:count_1\ \SPIM_1:BSPIM:BitCounter\/count_1 \SPIM_1:BSPIM:load_rx_data\/main_3 3.118
macrocell1 U(1,1) 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/main_3 \SPIM_1:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_1:BSPIM:load_rx_data\ \SPIM_1:BSPIM:load_rx_data\/q \SPIM_1:BSPIM:sR8:Dp:u0\/f1_load 2.652
datapathcell1 U(1,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 1.850
Clock Skew 0.000
\SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:RxStsReg\/status_6 77.131 MHz 12.965 487.035
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \SPIM_1:BSPIM:BitCounter\ \SPIM_1:BSPIM:BitCounter\/clock \SPIM_1:BSPIM:BitCounter\/count_2 2.110
Route 1 \SPIM_1:BSPIM:count_2\ \SPIM_1:BSPIM:BitCounter\/count_2 \SPIM_1:BSPIM:rx_status_6\/main_2 3.693
macrocell4 U(1,0) 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/main_2 \SPIM_1:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_1:BSPIM:rx_status_6\ \SPIM_1:BSPIM:rx_status_6\/q \SPIM_1:BSPIM:RxStsReg\/status_6 2.242
statusicell2 U(1,0) 1 \SPIM_1:BSPIM:RxStsReg\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 3.478
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/clock_0 \SPIM_1:BSPIM:load_cond\/q 1.250
macrocell11 U(1,0) 1 \SPIM_1:BSPIM:load_cond\ \SPIM_1:BSPIM:load_cond\/q \SPIM_1:BSPIM:load_cond\/main_8 2.228
macrocell11 U(1,0) 1 \SPIM_1:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
Net_59/q Net_59/main_3 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 Net_59 Net_59/clock_0 Net_59/q 1.250
macrocell10 U(0,0) 1 Net_59 Net_59/q Net_59/main_3 2.232
macrocell10 U(0,0) 1 Net_59 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 4.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_2\/main_9 2.777
macrocell7 U(1,1) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 4.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:state_1\/main_9 2.777
macrocell8 U(1,1) 1 \SPIM_1:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 4.027
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q \SPIM_1:BSPIM:ld_ident\/main_8 2.777
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:ld_ident\/q Net_57/main_10 4.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/clock_0 \SPIM_1:BSPIM:ld_ident\/q 1.250
Route 1 \SPIM_1:BSPIM:ld_ident\ \SPIM_1:BSPIM:ld_ident\/q Net_57/main_10 2.784
macrocell6 U(1,1) 1 Net_57 HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_0\/main_2 4.181
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 1.250
macrocell9 U(0,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_0\/main_2 2.931
macrocell9 U(0,1) 1 \SPIM_1:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_0 4.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 1.250
Route 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:sR8:Dp:u0\/cs_addr_0 2.964
datapathcell1 U(1,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:cnt_enable\/main_3 4.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(1,0) 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/clock_0 \SPIM_1:BSPIM:cnt_enable\/q 1.250
macrocell13 U(1,0) 1 \SPIM_1:BSPIM:cnt_enable\ \SPIM_1:BSPIM:cnt_enable\/q \SPIM_1:BSPIM:cnt_enable\/main_3 2.980
macrocell13 U(1,0) 1 \SPIM_1:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_2\/main_2 4.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,1) 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/clock_0 \SPIM_1:BSPIM:state_0\/q 1.250
Route 1 \SPIM_1:BSPIM:state_0\ \SPIM_1:BSPIM:state_0\/q \SPIM_1:BSPIM:state_2\/main_2 3.087
macrocell7 U(1,1) 1 \SPIM_1:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ SPIM_1_IntClock
Source Destination Delay (ns)
Pin_1(0)_PAD \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 22.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 Pin_1(0)_PAD Pin_1(0)_PAD Pin_1(0)/pad_in 0.000
iocell5 P0[5] 1 Pin_1(0) Pin_1(0)/pad_in Pin_1(0)/fb 10.483
Route 1 Net_60 Pin_1(0)/fb \SPIM_1:BSPIM:sR8:Dp:u0\/route_si 5.522
datapathcell1 U(1,1) 1 \SPIM_1:BSPIM:sR8:Dp:u0\ SETUP 6.780
Clock Clock path delay 0.000
+ Clock To Output Section
+ SPIM_1_IntClock
Source Destination Delay (ns)
Net_58/q Pin_3(0)_PAD 21.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 Net_58 Net_58/clock_0 Net_58/q 1.250
Route 1 Net_58 Net_58/q Pin_3(0)/pin_input 6.110
iocell7 P1[3] 1 Pin_3(0) Pin_3(0)/pin_input Pin_3(0)/pad_out 14.387
Route 1 Pin_3(0)_PAD Pin_3(0)/pad_out Pin_3(0)_PAD 0.000
Clock Clock path delay 0.000
Net_57/q Pin_2(0)_PAD 21.458
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,1) 1 Net_57 Net_57/clock_0 Net_57/q 1.250
Route 1 Net_57 Net_57/q Pin_2(0)/pin_input 6.196
iocell6 P0[4] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 14.012
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000