Static Timing Analysis

Project : CharLCD_CustomFont01
Build Time : 02/08/21 18:24:20
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 5.50
VDDA_CTB : 5.50
VDDD_0 : 5.50
VDDIO_0 : 5.50
VDDIO_1 : 5.50
VDDIO_2 : 5.50
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 5.5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFClk CyHFClk 48.000 MHz 48.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFClk CyLFClk 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySysClk CySysClk 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A