Static Timing Analysis

Project : DS18x8_demo
Build Time : 06/02/18 13:22:23
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 5.00
VDDD : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFClk CyHFClk 24.000 MHz 24.000 MHz N/A
UART_1_IntClock CyHFClk 76.677 kHz 76.677 kHz 45.865 MHz
Clock_ReportTimer CyHFClk 1.000  Hz 1.000  Hz 142.552 MHz
OneWire_clock_delay CyHFClk 1.000 kHz 1.000 kHz 38.450 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFClk CyLFClk 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySysClk CySysClk 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 1e+009ns(1  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FreqDiv_1:not_last_reset\/q Net_1071/main_1 142.552 MHz 7.015 999999992.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q Net_1071/main_1 2.255
macrocell21 U(0,0) 1 Net_1071 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 142.552 MHz 7.015 999999992.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 2.255
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 142.552 MHz 7.015 999999992.985
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 2.255
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_0\/q Net_1071/main_3 142.816 MHz 7.002 999999992.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q Net_1071/main_3 2.242
macrocell21 U(0,0) 1 Net_1071 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 142.816 MHz 7.002 999999992.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 2.242
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_1\/q Net_1071/main_2 142.857 MHz 7.000 999999993.000
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q Net_1071/main_2 2.240
macrocell21 U(0,0) 1 Net_1071 SETUP 3.510
Clock Skew 0.000
Net_1071/q Net_1071/main_0 142.898 MHz 6.998 999999993.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,0) 1 Net_1071 Net_1071/clock_0 Net_1071/q 1.250
macrocell21 U(0,0) 1 Net_1071 Net_1071/q Net_1071/main_0 2.238
macrocell21 U(0,0) 1 Net_1071 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 38.450 MHz 26.008 999973.992
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \OneWire:TimerDelay:TimerUDB:control_4\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 2.716
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 40.815 MHz 24.501 999975.499
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 2.539
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 41.327 MHz 24.197 999975.803
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/clock_0 \OneWire:TimerDelay:TimerUDB:timer_enable\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:trig_reg\/main_1 2.235
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_1 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/z0 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 42.795 MHz 23.367 999976.633
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/clock \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/z0 2.320
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.z0__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/z0 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0i 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0i \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0_comb 2.960
Route 1 \OneWire:TimerDelay:TimerUDB:per_zero\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0_comb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.287
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 43.999 MHz 22.728 999977.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \OneWire:TimerDelay:TimerUDB:control_4\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 2.716
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 44.002 MHz 22.726 999977.274
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 2.580
Route 1 \OneWire:TimerDelay:TimerUDB:control_4\ \OneWire:TimerDelay:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_4 \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 2.716
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_0 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.560
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0_comb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 45.585 MHz 21.937 999978.063
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/clock \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0_comb 3.850
Route 1 \OneWire:TimerDelay:TimerUDB:per_zero\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/z0_comb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 3.287
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_0 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 9.710
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 5.090
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 47.123 MHz 21.221 999978.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 2.539
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 47.128 MHz 21.219 999978.781
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 2.539
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_2 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/cs_addr_1 2.560
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ SETUP 11.520
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 47.808 MHz 20.917 999979.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/clock_0 \OneWire:TimerDelay:TimerUDB:timer_enable\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:trig_reg\/main_1 2.235
macrocell2 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/main_1 \OneWire:TimerDelay:TimerUDB:trig_reg\/q 3.350
Route 1 \OneWire:TimerDelay:TimerUDB:trig_reg\ \OneWire:TimerDelay:TimerUDB:trig_reg\/q \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/cs_addr_1 2.562
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ SETUP 11.520
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.865 MHz 21.803 13019.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.359
macrocell5 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.324
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.091 MHz 21.696 13019.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.252
macrocell5 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.324
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.808 MHz 21.364 13020.303
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 2.920
macrocell5 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.324
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.250 MHz 21.164 13020.503
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 2.970
macrocell5 U(0,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.324
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 63.379 MHz 15.778 13025.889
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 3.255
macrocell6 U(0,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 76.289 MHz 13.108 13028.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/so_comb 7.280
Route 1 \UART_1:BUART:tx_shift_out\ \UART_1:BUART:sTX:TxShifter:u0\/so_comb \UART_1:BUART:txn\/main_3 2.318
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_3 83.022 MHz 12.045 13029.622
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_state_0\/main_3 3.255
macrocell18 U(0,1) 1 \UART_1:BUART:tx_state_0\ SETUP 3.510
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:TxSts\/status_0 85.346 MHz 11.717 13029.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:tx_status_0\/main_1 3.224
macrocell6 U(0,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_1 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:TxSts\/status_0 86.170 MHz 11.605 13030.062
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:tx_status_0\/main_0 3.112
macrocell6 U(0,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_0 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:TxSts\/status_0 86.468 MHz 11.565 13030.102
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_status_0\/main_4 3.072
macrocell6 U(0,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_4 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.323
statusicell2 U(0,1) 1 \UART_1:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Net_1071/q Net_1071/main_0 3.488
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,0) 1 Net_1071 Net_1071/clock_0 Net_1071/q 1.250
macrocell21 U(0,0) 1 Net_1071 Net_1071/q Net_1071/main_0 2.238
macrocell21 U(0,0) 1 Net_1071 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_1\/q Net_1071/main_2 3.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/clock_0 \FreqDiv_1:count_1\/q 1.250
Route 1 \FreqDiv_1:count_1\ \FreqDiv_1:count_1\/q Net_1071/main_2 2.240
macrocell21 U(0,0) 1 Net_1071 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q Net_1071/main_3 3.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q Net_1071/main_3 2.242
macrocell21 U(0,0) 1 Net_1071 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 3.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/clock_0 \FreqDiv_1:count_0\/q 1.250
Route 1 \FreqDiv_1:count_0\ \FreqDiv_1:count_0\/q \FreqDiv_1:count_1\/main_1 2.242
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q Net_1071/main_1 3.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q Net_1071/main_1 2.255
macrocell21 U(0,0) 1 Net_1071 HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 3.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_1\/main_0 2.255
macrocell23 U(0,0) 1 \FreqDiv_1:count_1\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 3.505
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/clock_0 \FreqDiv_1:not_last_reset\/q 1.250
Route 1 \FreqDiv_1:not_last_reset\ \FreqDiv_1:not_last_reset\/q \FreqDiv_1:count_0\/main_0 2.255
macrocell24 U(0,0) 1 \FreqDiv_1:count_0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 3.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/clock \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb 3.210
Route 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0.co_msb__sig\ \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u0\/co_msb \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\/ci 0.000
datapathcell2 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:sT16:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_disable\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_6 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ \OneWire:TimerDelay:TimerUDB:trig_disable\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_disable\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ \OneWire:TimerDelay:TimerUDB:trig_disable\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_6 2.231
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_disable\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_5 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ \OneWire:TimerDelay:TimerUDB:trig_disable\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_disable\/q 1.250
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ \OneWire:TimerDelay:TimerUDB:trig_disable\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_5 2.231
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_2 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/clock_0 \OneWire:TimerDelay:TimerUDB:timer_enable\/q 1.250
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_2 2.235
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_1 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/clock_0 \OneWire:TimerDelay:TimerUDB:timer_enable\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ \OneWire:TimerDelay:TimerUDB:timer_enable\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_1 2.235
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_fall_detected\/q \OneWire:TimerDelay:TimerUDB:trig_fall_detected\/main_5 3.485
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_fall_detected\ \OneWire:TimerDelay:TimerUDB:trig_fall_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_fall_detected\/q 1.250
macrocell15 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_fall_detected\ \OneWire:TimerDelay:TimerUDB:trig_fall_detected\/q \OneWire:TimerDelay:TimerUDB:trig_fall_detected\/main_5 2.235
macrocell15 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_fall_detected\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_7 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:timer_enable\/main_7 2.539
macrocell11 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:timer_enable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_6 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_disable\/main_6 2.539
macrocell12 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_disable\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/main_5 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/main_5 2.539
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ HOLD 0.000
Clock Skew 0.000
\OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q LED/main_3 3.793
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/clock_0 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q 1.250
Route 1 \OneWire:TimerDelay:TimerUDB:trig_rise_detected\ \OneWire:TimerDelay:TimerUDB:trig_rise_detected\/q LED/main_3 2.543
macrocell10 U(1,0) 1 LED HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 3.558
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q \UART_1:BUART:txn\/main_0 2.308
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 3.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.810
macrocell17 U(0,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 3.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.810
macrocell19 U(0,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 3.812
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.812
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 3.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_1\/main_2 2.970
macrocell17 U(0,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 3.970
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_2\/main_2 2.970
macrocell19 U(0,1) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 4.092
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 3.092
datapathcell3 U(0,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 4.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_state_0\/main_2 3.098
macrocell18 U(0,1) 1 \UART_1:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 4.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(1,1) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:tx_bitclk\/main_2 3.098
macrocell20 U(0,1) 1 \UART_1:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_3 4.170
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:tx_state_1\/main_3 2.920
macrocell17 U(0,1) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ CyHFClk
Source Destination Delay (ns)
\OneWire:ControlReg_DRV:Sync:ctrl_reg\/control_0 Pin_0(0)_PAD:out 23.376
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(0,1) 1 \OneWire:ControlReg_DRV:Sync:ctrl_reg\ \OneWire:ControlReg_DRV:Sync:ctrl_reg\/busclk \OneWire:ControlReg_DRV:Sync:ctrl_reg\/control_0 2.580
Route 1 \OneWire:Net_1111\ \OneWire:ControlReg_DRV:Sync:ctrl_reg\/control_0 Pin_0(0)/pin_input 5.716
iocell1 P3[0] 1 Pin_0(0) Pin_0(0)/pin_input Pin_0(0)/pad_out 15.080
Route 1 Pin_0(0)_PAD Pin_0(0)/pad_out Pin_0(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ OneWire_clock_delay
Source Destination Delay (ns)
LED/q PinLED(0)_PAD 31.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 LED LED/clock_0 LED/q 1.250
Route 1 LED LED/q Net_2188/main_0 5.505
macrocell3 U(1,1) 1 Net_2188 Net_2188/main_0 Net_2188/q 3.350
Route 1 Net_2188 Net_2188/q PinLED(0)/pin_input 5.703
iocell2 P1[6] 1 PinLED(0) PinLED(0)/pin_input PinLED(0)/pad_out 15.420
Route 1 PinLED(0)_PAD PinLED(0)/pad_out PinLED(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_06(0)_PAD 27.468
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(1,1) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_39/main_0 2.308
macrocell4 U(1,1) 1 Net_39 Net_39/main_0 Net_39/q 3.350
Route 1 Net_39 Net_39/q Tx_06(0)/pin_input 5.950
iocell3 P0[5] 1 Tx_06(0) Tx_06(0)/pin_input Tx_06(0)/pad_out 14.610
Route 1 Tx_06(0)_PAD Tx_06(0)/pad_out Tx_06(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock To Output Enable Section
+ CyHFClk
Source Destination Type Delay (ns)
\OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 Pin_0(0)_PAD:out TURN ON 21.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \OneWire:ControlReg_SEL:Sync:ctrl_reg\ \OneWire:ControlReg_SEL:Sync:ctrl_reg\/busclk \OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 2.580
Route 1 \OneWire:tmpOE__bufoe_1_net_0\ \OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 Pin_0(0)/oe 4.906
iocell1 P3[0] 1 Pin_0(0) Pin_0(0)/oe Pin_0(0)/pad_out 13.874
Route 1 Pin_0(0)_PAD Pin_0(0)/pad_out Pin_0(0)_PAD:out 0.000
Clock Clock path delay 0.000
\OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 Pin_0(0)_PAD:out TURN OFF 21.360
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(0,0) 1 \OneWire:ControlReg_SEL:Sync:ctrl_reg\ \OneWire:ControlReg_SEL:Sync:ctrl_reg\/busclk \OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 2.580
Route 1 \OneWire:tmpOE__bufoe_1_net_0\ \OneWire:ControlReg_SEL:Sync:ctrl_reg\/control_0 Pin_0(0)/oe 4.906
iocell1 P3[0] 1 Pin_0(0) Pin_0(0)/oe Pin_0(0)/pad_out 13.874
Route 1 Pin_0(0)_PAD Pin_0(0)/pad_out Pin_0(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 1e+006ns(1 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
LED/q \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\/reset 149.254 MHz 6.700 999993.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 LED LED/clock_0 LED/q 1.250
Route 1 LED LED/q \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\/reset 5.450
statusicell1 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
LED/q \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\/reset 6.700
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 LED LED/clock_0 LED/q 1.250
Route 1 LED LED/q \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\/reset 5.450
statusicell1 U(0,0) 1 \OneWire:TimerDelay:TimerUDB:rstSts:stsreg\ REMOVAL 0.000
Clock Skew 0.000