Static Timing Analysis

Project : PSoC 4 Pioneer Modbus Slave
Build Time : 01/27/14 14:47:03
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK CyHFCLK 115.385 kHz 115.385 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 115.385 kHz 115.385 kHz N/A