# Static Timing Analysis

Project : | ABB Datalogger S1
Build Time : | 10/24/17 14:49:11
Device : | CY8C4247AZI-M485
Temperature : | -40C - 85C
VDDA_0 : | 3.30
VDDA_CTB : | 3.30
VDDD : | 3.30
VDDD_0 : | 3.30
VDDD_1 : | 3.30
VDDIO : | 3.30
VDDIO_1 : | 3.30
VDDIO_2 : | 3.30
VDDIO_A : | 3.30
VDDIO_A_1 : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
ADC_intClock(FFB) | ADC_intClock(FFB) | 2.143 MHz | 2.143 MHz | N/A |
CyHFCLK | CyHFCLK | 30.000 MHz | 30.000 MHz | 43.350 MHz |
ADC_intClock | CyHFCLK | 2.143 MHz | 2.143 MHz | N/A |
CyILO | CyILO | 32.000 kHz | 32.000 kHz | N/A |
CyIMO | CyIMO | 30.000 MHz | 30.000 MHz | N/A |
CyLFCLK | CyLFCLK | 32.000 kHz | 32.000 kHz | N/A |
CyRouted1 | CyRouted1 | 30.000 MHz | 30.000 MHz | N/A |
CySYSCLK | CySYSCLK | 30.000 MHz | 30.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : CyHFCLK : Positive edge(Required Frequency 30 MHz)
+ Destination Clock : CyHFCLK : Positive edge(Required Frequency 30 MHz)
Path Delay Requirement : 33.3333ns(30 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 43.350 MHz | 23.068 | 10.265 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 46.215 MHz | 21.638 | 11.695 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 49.356 MHz | 20.261 | 13.072 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.881
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 9.710
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 5.090
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 50.536 MHz | 19.788 | 13.545 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 50.914 MHz | 19.641 | 13.692 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.841
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 54.472 MHz | 18.358 | 14.975 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 54.912 MHz | 18.211 | 15.122 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.850
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.841
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 58.360 MHz | 17.135 | 16.198 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 3.035
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 58.889 MHz | 16.981 | 16.352 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.580
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.881
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | SETUP | 11.520
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:rstSts:stsreg\/status_0 | 64.700 MHz | 15.456 | 17.877 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 2.320
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.960
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:status_tc\/main_1 | 3.005
macrocell2 | U(0,0) | 1 | \Timer_1:TimerUDB:status_tc\ | \Timer_1:TimerUDB:status_tc\/main_1 | \Timer_1:TimerUDB:status_tc\/q | 3.350
Route |  | 1 | \Timer_1:TimerUDB:status_tc\ | \Timer_1:TimerUDB:status_tc\/q | \Timer_1:TimerUDB:rstSts:stsreg\/status_0 | 2.251
statusicell1 | U(0,0) | 1 | \Timer_1:TimerUDB:rstSts:stsreg\ |  | SETUP | 1.570
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : CyHFCLK : Positive edge
+ Destination Clock : CyHFCLK : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 3.210 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | 3.210
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.co_msb__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/co_msb | \Timer_1:TimerUDB:sT16:timerdp:u1\/ci | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 4.921 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_1 | 2.881
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 5.075 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_1 | 3.035
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_208/main_0 | 5.091 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(0,0) | 1 | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | 2.040
Route |  | 1 | \Timer_1:TimerUDB:control_7\ | \Timer_1:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 | Net_208/main_0 | 3.051
macrocell3 | U(0,0) | 1 | Net_208 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 6.111 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.270
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.841
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 6.258 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.270
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | Net_208/main_1 | 6.275 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/clock | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 3.270
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | Net_208/main_1 | 3.005
macrocell3 | U(0,0) | 1 | Net_208 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 7.321 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 1.740
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.740
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u1\/cs_addr_0 | 2.841
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 7.468 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 1.740
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.740
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | \Timer_1:TimerUDB:sT16:timerdp:u0\/cs_addr_0 | 2.988
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | Net_208/main_1 | 7.485 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
datapathcell1 | U(1,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/clock | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | 1.740
Route |  | 1 | \Timer_1:TimerUDB:sT16:timerdp:u0.z0__sig\ | \Timer_1:TimerUDB:sT16:timerdp:u0\/z0 | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | 0.000
datapathcell2 | U(0,0) | 1 | \Timer_1:TimerUDB:sT16:timerdp:u1\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0i | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | 2.740
Route |  | 1 | \Timer_1:TimerUDB:per_zero\ | \Timer_1:TimerUDB:sT16:timerdp:u1\/z0_comb | Net_208/main_1 | 3.005
macrocell3 | U(0,0) | 1 | Net_208 |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000