Static Timing Analysis

Project : 049_RotaryEncoder_SW_Dynamik_LotharMiller
Build Time : 11/22/15 02:37:03
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 81.900 MHz
Clock_2 CyHFCLK 50.000  Hz 50.000  Hz 81.900 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
PinEncSw(0)/fb Net_478/main_0 81.900 MHz 12.210 29.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell11 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 4.047
Route 1 Net_461 PinEncSw(0)/fb Net_478/main_0 4.653
macrocell1 U(1,1) 1 Net_478 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
PinEncSw(0)/fb Net_478/main_0 7.393
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell11 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 2.740
Route 1 Net_461 PinEncSw(0)/fb Net_478/main_0 4.653
macrocell1 U(1,1) 1 Net_478 HOLD 0.000
Clock Skew 0.000