Static Timing Analysis

Project : 049_RotaryEncoder_HW_debounced_1
Build Time : 11/20/15 01:49:58
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
Clock_3(FFB) Clock_3(FFB) 12.000 MHz 12.000 MHz N/A
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 81.619 MHz
Clock_1 CyHFCLK 2.000 kHz 2.000 kHz 81.619 MHz
Clock_3 CyHFCLK 12.000 MHz 12.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500000ns(2 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_467_1/q Net_467_1/main_0 121.168 MHz 8.253 499991.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,1) 1 Net_467_1 Net_467_1/clock_0 Net_467_1/q 1.250
macrocell4 U(1,1) 1 Net_467_1 Net_467_1/q Net_467_1/main_0 3.493
macrocell4 U(1,1) 1 Net_467_1 SETUP 3.510
Clock Skew 0.000
Net_467_2/q Net_467_2/main_1 121.403 MHz 8.237 499991.763
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,1) 1 Net_467_2 Net_467_2/clock_0 Net_467_2/q 1.250
macrocell6 U(1,1) 1 Net_467_2 Net_467_2/q Net_467_2/main_1 3.477
macrocell6 U(1,1) 1 Net_467_2 SETUP 3.510
Clock Skew 0.000
Net_467_0/q Net_467_0/main_0 141.363 MHz 7.074 499992.926
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,1) 1 Net_467_0 Net_467_0/clock_0 Net_467_0/q 1.250
macrocell2 U(1,1) 1 Net_467_0 Net_467_0/q Net_467_0/main_0 2.314
macrocell2 U(1,1) 1 Net_467_0 SETUP 3.510
Clock Skew 0.000
\GlitchFilter_1:genblk1[1]:sample\/q Net_467_1/main_2 141.423 MHz 7.071 499992.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,1) 1 \GlitchFilter_1:genblk1[1]:sample\ \GlitchFilter_1:genblk1[1]:sample\/clock_0 \GlitchFilter_1:genblk1[1]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[1]:sample\ \GlitchFilter_1:genblk1[1]:sample\/q Net_467_1/main_2 2.311
macrocell4 U(1,1) 1 Net_467_1 SETUP 3.510
Clock Skew 0.000
\GlitchFilter_1:genblk1[0]:sample\/q Net_467_0/main_2 141.643 MHz 7.060 499992.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(1,1) 1 \GlitchFilter_1:genblk1[0]:sample\ \GlitchFilter_1:genblk1[0]:sample\/clock_0 \GlitchFilter_1:genblk1[0]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[0]:sample\ \GlitchFilter_1:genblk1[0]:sample\/q Net_467_0/main_2 2.300
macrocell2 U(1,1) 1 Net_467_0 SETUP 3.510
Clock Skew 0.000
\GlitchFilter_1:genblk1[2]:sample\/q Net_467_2/main_2 141.924 MHz 7.046 499992.954
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,1) 1 \GlitchFilter_1:genblk1[2]:sample\ \GlitchFilter_1:genblk1[2]:sample\/clock_0 \GlitchFilter_1:genblk1[2]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[2]:sample\ \GlitchFilter_1:genblk1[2]:sample\/q Net_467_2/main_2 2.286
macrocell6 U(1,1) 1 Net_467_2 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
PinEncSw(0)/fb \GlitchFilter_1:genblk1[2]:sample\/main_0 81.619 MHz 12.252 29.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 4.047
Route 1 Net_481_2 PinEncSw(0)/fb \GlitchFilter_1:genblk1[2]:sample\/main_0 4.695
macrocell5 U(1,1) 1 \GlitchFilter_1:genblk1[2]:sample\ SETUP 3.510
Clock Skew 0.000
PinEncSw(0)/fb Net_467_2/main_0 81.619 MHz 12.252 29.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 4.047
Route 1 Net_481_2 PinEncSw(0)/fb Net_467_2/main_0 4.695
macrocell6 U(1,1) 1 Net_467_2 SETUP 3.510
Clock Skew 0.000
ENCA(0)/fb \GlitchFilter_1:genblk1[1]:sample\/main_0 81.813 MHz 12.223 29.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P2[0] 1 ENCA(0) ENCA(0)/in_clock ENCA(0)/fb 4.047
Route 1 Net_481_1 ENCA(0)/fb \GlitchFilter_1:genblk1[1]:sample\/main_0 4.666
macrocell3 U(1,1) 1 \GlitchFilter_1:genblk1[1]:sample\ SETUP 3.510
Clock Skew 0.000
ENCA(0)/fb Net_467_1/main_1 81.813 MHz 12.223 29.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P2[0] 1 ENCA(0) ENCA(0)/in_clock ENCA(0)/fb 4.047
Route 1 Net_481_1 ENCA(0)/fb Net_467_1/main_1 4.666
macrocell4 U(1,1) 1 Net_467_1 SETUP 3.510
Clock Skew 0.000
ENCB(0)/fb \GlitchFilter_1:genblk1[0]:sample\/main_0 81.873 MHz 12.214 29.453
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P2[1] 1 ENCB(0) ENCB(0)/in_clock ENCB(0)/fb 4.047
Route 1 Net_481_0 ENCB(0)/fb \GlitchFilter_1:genblk1[0]:sample\/main_0 4.657
macrocell1 U(1,1) 1 \GlitchFilter_1:genblk1[0]:sample\ SETUP 3.510
Clock Skew 0.000
ENCB(0)/fb Net_467_0/main_1 81.873 MHz 12.214 29.453
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P2[1] 1 ENCB(0) ENCB(0)/in_clock ENCB(0)/fb 4.047
Route 1 Net_481_0 ENCB(0)/fb Net_467_0/main_1 4.657
macrocell2 U(1,1) 1 Net_467_0 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\GlitchFilter_1:genblk1[2]:sample\/q Net_467_2/main_2 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(1,1) 1 \GlitchFilter_1:genblk1[2]:sample\ \GlitchFilter_1:genblk1[2]:sample\/clock_0 \GlitchFilter_1:genblk1[2]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[2]:sample\ \GlitchFilter_1:genblk1[2]:sample\/q Net_467_2/main_2 2.286
macrocell6 U(1,1) 1 Net_467_2 HOLD 0.000
Clock Skew 0.000
\GlitchFilter_1:genblk1[0]:sample\/q Net_467_0/main_2 3.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(1,1) 1 \GlitchFilter_1:genblk1[0]:sample\ \GlitchFilter_1:genblk1[0]:sample\/clock_0 \GlitchFilter_1:genblk1[0]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[0]:sample\ \GlitchFilter_1:genblk1[0]:sample\/q Net_467_0/main_2 2.300
macrocell2 U(1,1) 1 Net_467_0 HOLD 0.000
Clock Skew 0.000
\GlitchFilter_1:genblk1[1]:sample\/q Net_467_1/main_2 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell3 U(1,1) 1 \GlitchFilter_1:genblk1[1]:sample\ \GlitchFilter_1:genblk1[1]:sample\/clock_0 \GlitchFilter_1:genblk1[1]:sample\/q 1.250
Route 1 \GlitchFilter_1:genblk1[1]:sample\ \GlitchFilter_1:genblk1[1]:sample\/q Net_467_1/main_2 2.311
macrocell4 U(1,1) 1 Net_467_1 HOLD 0.000
Clock Skew 0.000
Net_467_0/q Net_467_0/main_0 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell2 U(1,1) 1 Net_467_0 Net_467_0/clock_0 Net_467_0/q 1.250
macrocell2 U(1,1) 1 Net_467_0 Net_467_0/q Net_467_0/main_0 2.314
macrocell2 U(1,1) 1 Net_467_0 HOLD 0.000
Clock Skew 0.000
Net_467_2/q Net_467_2/main_1 4.727
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell6 U(1,1) 1 Net_467_2 Net_467_2/clock_0 Net_467_2/q 1.250
macrocell6 U(1,1) 1 Net_467_2 Net_467_2/q Net_467_2/main_1 3.477
macrocell6 U(1,1) 1 Net_467_2 HOLD 0.000
Clock Skew 0.000
Net_467_1/q Net_467_1/main_0 4.743
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell4 U(1,1) 1 Net_467_1 Net_467_1/clock_0 Net_467_1/q 1.250
macrocell4 U(1,1) 1 Net_467_1 Net_467_1/q Net_467_1/main_0 3.493
macrocell4 U(1,1) 1 Net_467_1 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
ENCB(0)/fb \GlitchFilter_1:genblk1[0]:sample\/main_0 7.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P2[1] 1 ENCB(0) ENCB(0)/in_clock ENCB(0)/fb 2.740
Route 1 Net_481_0 ENCB(0)/fb \GlitchFilter_1:genblk1[0]:sample\/main_0 4.657
macrocell1 U(1,1) 1 \GlitchFilter_1:genblk1[0]:sample\ HOLD 0.000
Clock Skew 0.000
ENCB(0)/fb Net_467_0/main_1 7.397
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell9 P2[1] 1 ENCB(0) ENCB(0)/in_clock ENCB(0)/fb 2.740
Route 1 Net_481_0 ENCB(0)/fb Net_467_0/main_1 4.657
macrocell2 U(1,1) 1 Net_467_0 HOLD 0.000
Clock Skew 0.000
ENCA(0)/fb \GlitchFilter_1:genblk1[1]:sample\/main_0 7.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P2[0] 1 ENCA(0) ENCA(0)/in_clock ENCA(0)/fb 2.740
Route 1 Net_481_1 ENCA(0)/fb \GlitchFilter_1:genblk1[1]:sample\/main_0 4.666
macrocell3 U(1,1) 1 \GlitchFilter_1:genblk1[1]:sample\ HOLD 0.000
Clock Skew 0.000
ENCA(0)/fb Net_467_1/main_1 7.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell8 P2[0] 1 ENCA(0) ENCA(0)/in_clock ENCA(0)/fb 2.740
Route 1 Net_481_1 ENCA(0)/fb Net_467_1/main_1 4.666
macrocell4 U(1,1) 1 Net_467_1 HOLD 0.000
Clock Skew 0.000
PinEncSw(0)/fb \GlitchFilter_1:genblk1[2]:sample\/main_0 7.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 2.740
Route 1 Net_481_2 PinEncSw(0)/fb \GlitchFilter_1:genblk1[2]:sample\/main_0 4.695
macrocell5 U(1,1) 1 \GlitchFilter_1:genblk1[2]:sample\ HOLD 0.000
Clock Skew 0.000
PinEncSw(0)/fb Net_467_2/main_0 7.435
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell10 P2[4] 1 PinEncSw(0) PinEncSw(0)/in_clock PinEncSw(0)/fb 2.740
Route 1 Net_481_2 PinEncSw(0)/fb Net_467_2/main_0 4.695
macrocell6 U(1,1) 1 Net_467_2 HOLD 0.000
Clock Skew 0.000