Static Timing Analysis

Project : uart
Build Time : 01/09/17 15:22:36
Device : CY8C4247AZI-M485
Temperature : -40C - 85C
VDDA_0 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDD_0 : 3.30
VDDD_1 : 3.30
VDDIO : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 48.330 MHz
UART_IntClock CyHFCLK 1.846 MHz 1.846 MHz 42.709 MHz
UART_1_SCBCLK CyHFCLK 1.371 MHz 1.371 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
UART_1_SCBCLK(FFB) UART_1_SCBCLK(FFB) 1.371 MHz 1.371 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
RX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 48.330 MHz 20.691 0.142
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_postpoll\/main_0 5.839
macrocell7 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.245
datapathcell3 U(1,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_1\/main_6 50.284 MHz 19.887 0.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_1_split\/main_0 6.696
macrocell1 U(1,1) 1 \UART:BUART:pollcount_1_split\ \UART:BUART:pollcount_1_split\/main_0 \UART:BUART:pollcount_1_split\/q 3.350
Route 1 \UART:BUART:pollcount_1_split\ \UART:BUART:pollcount_1_split\/q \UART:BUART:pollcount_1\/main_6 2.284
macrocell23 U(1,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_1\/main_0 69.915 MHz 14.303 6.530
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_1\/main_0 6.746
macrocell23 U(1,1) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_0\/main_0 69.915 MHz 14.303 6.530
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_0\/main_0 6.746
macrocell24 U(1,1) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_state_0\/main_0 73.665 MHz 13.575 7.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_state_0\/main_0 6.018
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_status_3\/main_0 73.665 MHz 13.575 7.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_status_3\/main_0 6.018
macrocell25 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_state_2\/main_0 73.725 MHz 13.564 7.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_state_2\/main_0 6.007
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_last\/main_0 74.516 MHz 13.420 7.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 4.047
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_last\/main_0 5.863
macrocell26 U(1,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 541.667ns(1.84615 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 42.709 MHz 23.414 518.253
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.987
macrocell3 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.307
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.884 MHz 21.794 519.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.617
macrocell3 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.307
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.202 MHz 21.644 520.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.217
macrocell3 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.307
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 47.103 MHz 21.230 520.437
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(0,1) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.803
macrocell3 U(0,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.307
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 56.281 MHz 17.768 523.899
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 6.070
macrocell6 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.878
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 60.731 MHz 16.466 525.201
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,1) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 4.411
macrocell7 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.245
datapathcell3 U(1,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 60.861 MHz 16.431 525.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,0) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.228
macrocell8 U(1,0) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 4.003
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 60.968 MHz 16.402 525.265
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,1) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 4.347
macrocell7 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.245
datapathcell3 U(1,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.426 MHz 16.019 525.648
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,1) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.494
macrocell4 U(0,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.325
statusicell1 U(1,1) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 64.115 MHz 15.597 526.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.899
macrocell6 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.878
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
RX(0)/fb \UART:BUART:rx_last\/main_0 8.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_last\/main_0 5.863
macrocell26 U(1,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_state_2\/main_0 8.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_state_2\/main_0 6.007
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_state_0\/main_0 8.758
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_state_0\/main_0 6.018
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:rx_status_3\/main_0 8.758
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_status_3\/main_0 6.018
macrocell25 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_1\/main_0 9.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_1\/main_0 6.746
macrocell23 U(1,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_0\/main_0 9.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_0\/main_0 6.746
macrocell24 U(1,1) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:rx_postpoll\/main_0 5.839
macrocell7 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.245
datapathcell3 U(1,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
RX(0)/fb \UART:BUART:pollcount_1\/main_6 15.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[0] 1 RX(0) RX(0)/in_clock RX(0)/fb 2.740
Route 1 Net_94 RX(0)/fb \UART:BUART:pollcount_1_split\/main_0 6.696
macrocell1 U(1,1) 1 \UART:BUART:pollcount_1_split\ \UART:BUART:pollcount_1_split\/main_0 \UART:BUART:pollcount_1_split\/q 3.350
Route 1 \UART:BUART:pollcount_1_split\ \UART:BUART:pollcount_1_split\/q \UART:BUART:pollcount_1\/main_6 2.284
macrocell23 U(1,1) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.252
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 3.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(1,0) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 2.232
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:tx_state_0\/main_1 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:tx_state_0\/main_1 2.243
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:tx_bitclk\/main_1 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:tx_bitclk\/main_1 2.243
macrocell14 U(1,0) 1 \UART:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell10 U(0,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.314
macrocell10 U(0,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.606
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.606
macrocell11 U(0,1) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.606
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.606
macrocell13 U(0,1) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.618
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.618
macrocell10 U(0,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:tx_bitclk\/q \UART:BUART:tx_state_0\/main_5 3.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,0) 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/clock_0 \UART:BUART:tx_bitclk\/q 1.250
Route 1 \UART:BUART:tx_bitclk\ \UART:BUART:tx_bitclk\/q \UART:BUART:tx_state_0\/main_5 2.535
macrocell12 U(1,0) 1 \UART:BUART:tx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_5 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_5 2.539
macrocell16 U(0,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q TX(0)_PAD 27.941
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_63/main_0 2.314
macrocell2 U(0,1) 1 Net_63 Net_63/main_0 Net_63/q 3.350
Route 1 Net_63 Net_63/q TX(0)/pin_input 5.847
iocell2 P1[1] 1 TX(0) TX(0)/pin_input TX(0)/pad_out 15.180
Route 1 TX(0)_PAD TX(0)/pad_out TX(0)_PAD 0.000
Clock Clock path delay 0.000