Static Timing Analysis

Project : Design01
Build Time : 03/25/17 21:20:35
Device : CY8C4247LQI-BL483
Temperature : -40C - 85C
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD_0 : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDR_BGLS : 3.30
VDDR_HF : 3.30
VDDR_HLS : 3.30
VDDR_LF : 3.30
VDDR_SYN : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyECO CyECO 24.000 MHz 24.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz 48.648 MHz
UART_IntClock CyHFCLK 76.800 kHz 76.800 kHz 43.048 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 20.8333ns(48 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 48.648 MHz 20.556 0.277
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.102
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 73.790 MHz 13.552 7.281
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.995
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 73.954 MHz 13.522 7.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.965
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 73.954 MHz 13.522 7.311
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.965
macrocell23 U(1,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 78.858 MHz 12.681 8.152
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.124
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 78.995 MHz 12.659 8.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.102
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 78.995 MHz 12.659 8.174
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 4.047
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.102
macrocell24 U(1,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13020.8ns(76.8 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.048 MHz 23.230 12997.603
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 5.118
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.242
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 43.495 MHz 22.991 12997.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 4.629
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.242
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.059 MHz 22.697 12998.136
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.335
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.242
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.224 MHz 22.612 12998.221
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 4.250
macrocell2 U(0,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.242
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 62.027 MHz 16.122 13004.711
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,1) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 4.975
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.069 MHz 16.111 13004.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.646
macrocell3 U(1,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.265
statusicell1 U(1,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 62.069 MHz 16.111 13004.722
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 3.454
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 65.850 MHz 15.186 13005.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 2.529
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 67.435 MHz 14.829 13006.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.312
macrocell7 U(0,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 2.317
statusicell2 U(0,1) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:TxSts\/status_0 67.463 MHz 14.823 13006.010
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:tx_status_0\/main_4 6.388
macrocell3 U(1,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_4 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.265
statusicell1 U(1,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 7.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_2 5.102
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.102
macrocell24 U(1,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 7.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_3 5.124
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 8.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_9 5.965
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 8.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_6 5.965
macrocell23 U(1,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 8.735
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_8 5.995
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 14.039
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P1[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.740
Route 1 Net_26 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_1 5.102
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(1,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.567
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,1) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.317
statusicell2 U(0,1) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.528
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.528
macrocell12 U(0,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.536
macrocell9 U(0,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.536
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.536
macrocell10 U(0,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.772
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell9 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.522
macrocell9 U(0,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 3.778
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 2.528
macrocell21 U(1,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 3.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 2.529
macrocell22 U(1,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_2\/main_3 2.775
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_state_stop1_reg\/main_2 2.775
macrocell20 U(1,1) 1 \UART:BUART:rx_state_stop1_reg\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 4.041
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 2.791
macrocell15 U(1,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 27.664
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_21/main_0 3.265
macrocell1 U(0,1) 1 Net_21 Net_21/main_0 Net_21/q 3.350
Route 1 Net_21 Net_21/q Tx_1(0)/pin_input 5.740
iocell2 P1[5] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.059
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000