Static Timing Analysis

Project : CY8CKIT_046_CapSense_Buttons
Build Time : 04/10/19 11:00:58
Device : CY8C4248BZI-L489
Temperature : -40C - 85C
VBUS : 5.00
VDDA_0 : 3.30
VDDA_1 : 3.30
VDDA_CTB : 3.30
VDDD : 3.30
VDDIO : 3.30
VDDIO_0 : 3.30
VDDIO_1 : 3.30
VDDIO_2 : 3.30
VDDIO_3 : 3.30
VDDIO_4 : 3.30
VDDIO_A : 3.30
VDDIO_A_1 : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CapSense_Buttons_SampleClk(FFB) CapSense_Buttons_SampleClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_Buttons_SenseClk(FFB) CapSense_Buttons_SenseClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_Proximity_SampleClk(FFB) CapSense_Proximity_SampleClk(FFB) 188.235 kHz 188.235 kHz N/A
CapSense_Proximity_SenseClk(FFB) CapSense_Proximity_SenseClk(FFB) 188.235 kHz 188.235 kHz N/A
Clock_PWM(FFB) Clock_PWM(FFB) 48.000 MHz 48.000 MHz N/A
CyHFCLK CyHFCLK 48.000 MHz 48.000 MHz N/A
Clock_PWM CyHFCLK 48.000 MHz 48.000 MHz N/A
CapSense_Buttons_SampleClk CyHFCLK 188.235 kHz 188.235 kHz N/A
CapSense_Buttons_SenseClk CyHFCLK 188.235 kHz 188.235 kHz N/A
CapSense_Proximity_SampleClk CyHFCLK 188.235 kHz 188.235 kHz N/A
CapSense_Proximity_SenseClk CyHFCLK 188.235 kHz 188.235 kHz N/A
EZI2C_SCBCLK CyHFCLK 8.000 MHz 8.000 MHz N/A
UART_SCBCLK CyHFCLK 1.371 MHz 1.371 MHz N/A
CyIMO CyIMO 48.000 MHz 48.000 MHz N/A
CyLFCLK CyLFCLK 32.768 kHz 32.768 kHz N/A
CyRouted1 CyRouted1 48.000 MHz 48.000 MHz N/A
CySYSCLK CySYSCLK 48.000 MHz 48.000 MHz N/A
CyWCO CyWCO 32.768 kHz 32.768 kHz N/A
EZI2C_SCBCLK(FFB) EZI2C_SCBCLK(FFB) 8.000 MHz 8.000 MHz N/A
UART_SCBCLK(FFB) UART_SCBCLK(FFB) 1.371 MHz 1.371 MHz N/A
+ Clock To Output Section
+ Clock_PWM(FFB)
Source Destination Delay (ns)
\PWM_Green:cy_m0s8_tcpwm_1\/line Pin_GreenLED(0)_PAD 18.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,0) 1 \PWM_Green:cy_m0s8_tcpwm_1\ \PWM_Green:cy_m0s8_tcpwm_1\/clock \PWM_Green:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_1207 \PWM_Green:cy_m0s8_tcpwm_1\/line Pin_GreenLED(0)/pin_input 3.785
iocell9 P5[3] 1 Pin_GreenLED(0) Pin_GreenLED(0)/pin_input Pin_GreenLED(0)/pad_out 14.230
Route 1 Pin_GreenLED(0)_PAD Pin_GreenLED(0)/pad_out Pin_GreenLED(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_Red:cy_m0s8_tcpwm_1\/line Pin_RedLED(0)_PAD 14.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,5) 1 \PWM_Red:cy_m0s8_tcpwm_1\ \PWM_Red:cy_m0s8_tcpwm_1\/clock \PWM_Red:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_1144 \PWM_Red:cy_m0s8_tcpwm_1\/line Pin_RedLED(0)/pin_input 1.000
iocell10 P5[2] 1 Pin_RedLED(0) Pin_RedLED(0)/pin_input Pin_RedLED(0)/pad_out 13.950
Route 1 Pin_RedLED(0)_PAD Pin_RedLED(0)/pad_out Pin_RedLED(0)_PAD 0.000
Clock Clock path delay 0.000
\PWM_Blue:cy_m0s8_tcpwm_1\/line Pin_BlueLED(0)_PAD 14.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
m0s8tcpwmcell F(TCPWM,6) 1 \PWM_Blue:cy_m0s8_tcpwm_1\ \PWM_Blue:cy_m0s8_tcpwm_1\/clock \PWM_Blue:cy_m0s8_tcpwm_1\/line 0.000
Route 1 Net_1239 \PWM_Blue:cy_m0s8_tcpwm_1\/line Pin_BlueLED(0)/pin_input 1.000
iocell11 P5[4] 1 Pin_BlueLED(0) Pin_BlueLED(0)/pin_input Pin_BlueLED(0)/pad_out 13.850
Route 1 Pin_BlueLED(0)_PAD Pin_BlueLED(0)/pad_out Pin_BlueLED(0)_PAD 0.000
Clock Clock path delay 0.000