Static Timing Analysis

Project : testloopback
Build Time : 09/12/16 09:03:20
Device : CY8C5287AXI-LP095
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Hold
Clock_1 Net_31/q -1.886
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 80.000 MHz 80.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 80.000 MHz 80.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 80.000 MHz 80.000 MHz N/A
Clock_1 CyMASTER_CLK 10.000 MHz 10.000 MHz 36.580 MHz
Net_31/q CyMASTER_CLK UNKNOWN UNKNOWN 18.290 MHz
CyPLL_OUT CyPLL_OUT 80.000 MHz 80.000 MHz N/A
CyXTAL CyXTAL 10.000 MHz 10.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 100ns(10 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_32/q \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 68.222 MHz 14.658 85.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q Net_18/main_0 4.243
macrocell9 U(3,1) 1 Net_18 Net_18/main_0 Net_18/q 3.350
Route 1 Net_18 Net_18/q \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 2.315
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_3 \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 69.633 MHz 14.361 85.639
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_2:BSPIM:count_3\ \SPIM_2:BSPIM:BitCounter\/count_3 \SPIM_2:BSPIM:load_rx_data\/main_1 3.361
macrocell1 U(3,0) 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/main_1 \SPIM_2:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/q \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 2.860
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_2:BSPIM:state_0\/q \SPIM_2:BSPIM:TxStsReg\/status_0 70.131 MHz 14.259 85.741
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,2) 1 \SPIM_2:BSPIM:state_0\ \SPIM_2:BSPIM:state_0\/clock_0 \SPIM_2:BSPIM:state_0\/q 1.250
Route 1 \SPIM_2:BSPIM:state_0\ \SPIM_2:BSPIM:state_0\/q \SPIM_2:BSPIM:tx_status_0\/main_2 6.908
macrocell2 U(2,0) 1 \SPIM_2:BSPIM:tx_status_0\ \SPIM_2:BSPIM:tx_status_0\/main_2 \SPIM_2:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_2:BSPIM:tx_status_0\ \SPIM_2:BSPIM:tx_status_0\/q \SPIM_2:BSPIM:TxStsReg\/status_0 2.251
statusicell1 U(2,0) 1 \SPIM_2:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_4 \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 72.908 MHz 13.716 86.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_2:BSPIM:count_4\ \SPIM_2:BSPIM:BitCounter\/count_4 \SPIM_2:BSPIM:load_rx_data\/main_0 2.716
macrocell1 U(3,0) 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/main_0 \SPIM_2:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/q \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 2.860
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 73.041 MHz 13.691 86.309
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_2:BSPIM:count_2\ \SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:load_rx_data\/main_2 2.691
macrocell1 U(3,0) 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/main_2 \SPIM_2:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/q \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 2.860
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 73.790 MHz 13.552 86.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_2:BSPIM:count_0\ \SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:load_rx_data\/main_4 2.552
macrocell1 U(3,0) 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/main_4 \SPIM_2:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/q \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 2.860
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 73.795 MHz 13.551 86.449
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_2:BSPIM:count_1\ \SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:load_rx_data\/main_3 2.551
macrocell1 U(3,0) 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/main_3 \SPIM_2:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_2:BSPIM:load_rx_data\ \SPIM_2:BSPIM:load_rx_data\/q \SPIM_2:BSPIM:sR8:Dp:u0\/f1_load 2.860
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM_2:BSPIM:state_2\/q \SPIM_2:BSPIM:sR8:Dp:u0\/cs_addr_2 74.694 MHz 13.388 86.612
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,0) 1 \SPIM_2:BSPIM:state_2\ \SPIM_2:BSPIM:state_2\/clock_0 \SPIM_2:BSPIM:state_2\/q 1.250
Route 1 \SPIM_2:BSPIM:state_2\ \SPIM_2:BSPIM:state_2\/q \SPIM_2:BSPIM:sR8:Dp:u0\/cs_addr_2 6.128
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 6.010
Clock Skew 0.000
\SPIM_2:BSPIM:state_0\/q \SPIM_2:BSPIM:sR8:Dp:u0\/cs_addr_0 77.839 MHz 12.847 87.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,2) 1 \SPIM_2:BSPIM:state_0\ \SPIM_2:BSPIM:state_0\/clock_0 \SPIM_2:BSPIM:state_0\/q 1.250
Route 1 \SPIM_2:BSPIM:state_0\ \SPIM_2:BSPIM:state_0\/q \SPIM_2:BSPIM:sR8:Dp:u0\/cs_addr_0 5.587
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 6.010
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_3 \SPIM_2:BSPIM:RxStsReg\/status_6 78.321 MHz 12.768 87.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_2:BSPIM:count_3\ \SPIM_2:BSPIM:BitCounter\/count_3 \SPIM_2:BSPIM:rx_status_6\/main_1 4.653
macrocell4 U(3,1) 1 \SPIM_2:BSPIM:rx_status_6\ \SPIM_2:BSPIM:rx_status_6\/main_1 \SPIM_2:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM_2:BSPIM:rx_status_6\ \SPIM_2:BSPIM:rx_status_6\/q \SPIM_2:BSPIM:RxStsReg\/status_6 2.325
statusicell2 U(2,1) 1 \SPIM_2:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 100ns
Affects clock : Clock_1
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_30/q \SPIS_1:BSPIS:mosi_tmp\/main_0 369.549 MHz 2.706 97.294
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,0) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q \SPIS_1:BSPIS:mosi_tmp\/main_0 5.598
macrocell26 U(3,2) 1 \SPIS_1:BSPIS:mosi_tmp\ SETUP 3.510
Clock Skew -7.652
Path Delay Requirement : 100ns
Affects clock : Clock_1
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_32/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_2 82.727 MHz 12.088 87.912
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:inv_ss\/main_0 4.243
macrocell5 U(3,1) 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/main_0 \SPIS_1:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_2 5.489
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -6.724
Net_32/q \SPIS_1:BSPIS:BitCounter\/enable 85.712 MHz 11.667 88.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:inv_ss\/main_0 4.243
macrocell5 U(3,1) 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/main_0 \SPIS_1:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/q \SPIS_1:BSPIS:BitCounter\/enable 5.488
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ SETUP 4.060
Clock Skew -6.724
Net_30/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 119.646 MHz 8.358 91.642
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,0) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q \SPIS_1:BSPIS:mosi_to_dp\/main_0 5.598
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_0 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -6.724
Net_32/q \SPIS_1:BSPIS:BitCounter\/reset -1.886 101.886
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:BitCounter\/reset 3.588
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ RECOVERY -0.000
Clock Skew -6.724
Path Delay Requirement : 100ns
Affects clock : Clock_1
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_31/q Net_31/main_3 96.061 MHz 10.410 88.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
macrocell23 U(3,1) 1 Net_31 Net_31/q Net_31/main_3 6.900
macrocell23 U(3,1) 1 Net_31 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 100ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 78.777 MHz 12.694
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,2) 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/clock_0 \SPIS_1:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:mosi_to_dp\/main_5 2.282
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_5 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.928
Path Delay Requirement : 100ns
Affects clock : Clock_1
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:sR8:Dp:u0\/so_comb \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 36.580 MHz 27.337 72.663
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ \SPIS_1:BSPIS:sR8:Dp:u0\/clock \SPIS_1:BSPIS:sR8:Dp:u0\/so_comb 9.160
Route 1 \SPIS_1:BSPIS:miso_from_dp\ \SPIS_1:BSPIS:sR8:Dp:u0\/so_comb Net_18/main_1 2.288
macrocell9 U(3,1) 1 Net_18 Net_18/main_1 Net_18/q 3.350
Route 1 Net_18 Net_18/q \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 2.315
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Skew 6.724
Net_31/q Net_31/main_3 96.061 MHz 10.410 88.340
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
macrocell23 U(3,1) 1 Net_31 Net_31/q Net_31/main_3 6.900
macrocell23 U(3,1) 1 Net_31 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 100ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 79.994 MHz 12.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 3.811
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 85.092 MHz 11.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 85.092 MHz 11.752
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 85.150 MHz 11.744
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 3.054
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 0.000
Path Delay Requirement : 200ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 58.889 MHz 16.981
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 3.811
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 61.607 MHz 16.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 61.607 MHz 16.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 61.637 MHz 16.224
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 3.054
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 68.752 MHz 14.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:mosi_to_dp\/main_2 4.371
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_2 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 75.466 MHz 13.251
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:mosi_to_dp\/main_3 3.077
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_3 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 75.506 MHz 13.244
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:mosi_to_dp\/main_1 3.070
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_1 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 75.512 MHz 13.243
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:mosi_to_dp\/main_4 3.069
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_4 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:state_2\/main_7 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_2:BSPIM:count_0\ \SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:state_2\/main_7 2.543
macrocell16 U(3,0) 1 \SPIM_2:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:state_2\/main_6 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_2:BSPIM:count_1\ \SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:state_2\/main_6 2.543
macrocell16 U(3,0) 1 \SPIM_2:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:state_1\/main_6 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_2:BSPIM:count_1\ \SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:state_1\/main_6 2.543
macrocell17 U(3,0) 1 \SPIM_2:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:state_1\/main_7 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_2:BSPIM:count_0\ \SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:state_1\/main_7 2.543
macrocell17 U(3,0) 1 \SPIM_2:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:ld_ident\/main_6 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_2:BSPIM:count_1\ \SPIM_2:BSPIM:BitCounter\/count_1 \SPIM_2:BSPIM:ld_ident\/main_6 2.543
macrocell21 U(3,0) 1 \SPIM_2:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:ld_ident\/main_7 3.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_2:BSPIM:count_0\ \SPIM_2:BSPIM:BitCounter\/count_0 \SPIM_2:BSPIM:ld_ident\/main_7 2.543
macrocell21 U(3,0) 1 \SPIM_2:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_1 Net_30/main_8 3.171
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_2:BSPIM:count_1\ \SPIM_2:BSPIM:BitCounter\/count_1 Net_30/main_8 2.551
macrocell15 U(3,0) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_0 Net_30/main_9 3.172
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_2:BSPIM:count_0\ \SPIM_2:BSPIM:BitCounter\/count_0 Net_30/main_9 2.552
macrocell15 U(3,0) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:state_2\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_2:BSPIM:count_2\ \SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:state_2\/main_5 2.684
macrocell16 U(3,0) 1 \SPIM_2:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:state_1\/main_5 3.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIM_2:BSPIM:BitCounter\ \SPIM_2:BSPIM:BitCounter\/clock \SPIM_2:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_2:BSPIM:count_2\ \SPIM_2:BSPIM:BitCounter\/count_2 \SPIM_2:BSPIM:state_1\/main_5 2.684
macrocell17 U(3,0) 1 \SPIM_2:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_30/q \SPIS_1:BSPIS:mosi_tmp\/main_0 -0.804 HOLD
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,0) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q \SPIS_1:BSPIS:mosi_tmp\/main_0 5.598
macrocell26 U(3,2) 1 \SPIS_1:BSPIS:mosi_tmp\ HOLD 0.000
Clock Skew -7.652
Source Destination Slack (ns) Violation
Net_32/q \SPIS_1:BSPIS:BitCounter\/reset -1.886 REMOVAL
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:BitCounter\/reset 3.588
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ REMOVAL 0.000
Clock Skew -6.724
Net_30/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 4.818
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,0) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q \SPIS_1:BSPIS:mosi_to_dp\/main_0 5.598
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_0 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -6.724
Net_32/q \SPIS_1:BSPIS:BitCounter\/enable 7.607
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:inv_ss\/main_0 4.243
macrocell5 U(3,1) 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/main_0 \SPIS_1:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/q \SPIS_1:BSPIS:BitCounter\/enable 5.488
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ HOLD 0.000
Clock Skew -6.724
Net_32/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_2 7.608
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:inv_ss\/main_0 4.243
macrocell5 U(3,1) 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/main_0 \SPIS_1:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS_1:BSPIS:inv_ss\ \SPIS_1:BSPIS:inv_ss\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_2 5.489
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -6.724
Source Destination Slack (ns) Violation
Net_31/q Net_31/main_3 8.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
macrocell23 U(3,1) 1 Net_31 Net_31/q Net_31/main_3 6.900
macrocell23 U(3,1) 1 Net_31 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 109.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,2) 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/clock_0 \SPIS_1:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS_1:BSPIS:mosi_tmp\ \SPIS_1:BSPIS:mosi_tmp\/q \SPIS_1:BSPIS:mosi_to_dp\/main_5 2.282
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_5 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.928
Source Destination Slack (ns) Violation
Net_31/q Net_31/main_3 8.150
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
macrocell23 U(3,1) 1 Net_31 Net_31/q Net_31/main_3 6.900
macrocell23 U(3,1) 1 Net_31 HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:sR8:Dp:u0\/so_comb \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 20.457
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ \SPIS_1:BSPIS:sR8:Dp:u0\/clock \SPIS_1:BSPIS:sR8:Dp:u0\/so_comb 5.780
Route 1 \SPIS_1:BSPIS:miso_from_dp\ \SPIS_1:BSPIS:sR8:Dp:u0\/so_comb Net_18/main_1 2.288
macrocell9 U(3,1) 1 Net_18 Net_18/main_1 Net_18/q 3.350
Route 1 Net_18 Net_18/q \SPIM_2:BSPIM:sR8:Dp:u0\/route_si 2.315
datapathcell1 U(2,1) 1 \SPIM_2:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 6.724
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 107.034
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 3.054
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 107.042
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 107.042
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 107.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 3.811
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/f1_load 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 8.383
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:mosi_to_dp\/main_4 3.069
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_4 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 8.384
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:mosi_to_dp\/main_1 3.070
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_1 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 8.391
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:mosi_to_dp\/main_3 3.077
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_3 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 9.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:mosi_to_dp\/main_2 4.371
macrocell13 U(3,2) 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/main_2 \SPIS_1:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS_1:BSPIS:mosi_to_dp\ \SPIS_1:BSPIS:mosi_to_dp\/q \SPIS_1:BSPIS:sR8:Dp:u0\/route_si 2.914
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 10.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS_1:BSPIS:count_3\ \SPIS_1:BSPIS:BitCounter\/count_3 \SPIS_1:BSPIS:tx_load\/main_0 3.054
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_0 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 10.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS_1:BSPIS:count_1\ \SPIS_1:BSPIS:BitCounter\/count_1 \SPIS_1:BSPIS:tx_load\/main_2 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_2 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 10.432
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS_1:BSPIS:count_0\ \SPIS_1:BSPIS:BitCounter\/count_0 \SPIS_1:BSPIS:tx_load\/main_3 3.062
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_3 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
\SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 11.181
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ \SPIS_1:BSPIS:BitCounter\/clock_n \SPIS_1:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS_1:BSPIS:count_2\ \SPIS_1:BSPIS:BitCounter\/count_2 \SPIS_1:BSPIS:tx_load\/main_1 3.811
macrocell6 U(3,2) 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/main_1 \SPIS_1:BSPIS:tx_load\/q 3.350
Route 1 \SPIS_1:BSPIS:tx_load\ \SPIS_1:BSPIS:tx_load\/q \SPIS_1:BSPIS:sR8:Dp:u0\/cs_addr_0 3.400
datapathcell2 U(3,1) 1 \SPIS_1:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_32/q TP13(0)_PAD 23.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q TP13(0)/pin_input 7.128
iocell5 P15[3] 1 TP13(0) TP13(0)/pin_input TP13(0)/pad_out 15.486
Route 1 TP13(0)_PAD TP13(0)/pad_out TP13(0)_PAD 0.000
Clock Clock path delay 0.000
Net_30/q TP12(0)_PAD 23.742
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,0) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q TP12(0)/pin_input 6.637
iocell1 P12[0] 1 TP12(0) TP12(0)/pin_input TP12(0)/pad_out 15.855
Route 1 TP12(0)_PAD TP12(0)/pad_out TP12(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
DMA_1/termout TP14(0)_PAD 29.448
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell1 [DrqContainer=(0)][DrqId=(0)] 1 DMA_1 DMA_1/clock DMA_1/termout 9.000
Route 1 Net_68 DMA_1/termout TP14(0)/pin_input 5.828
iocell3 P3[0] 1 TP14(0) TP14(0)/pin_input TP14(0)/pad_out 14.620
Route 1 TP14(0)_PAD TP14(0)/pad_out TP14(0)_PAD 0.000
Clock Clock path delay 0.000
+ Net_31/q
Source Destination Delay (ns)
Net_31/q TP9(0)_PAD 25.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
Route 1 Net_31 Net_31/q TP9(0)/pin_input 11.313
iocell2 P6[5] 1 TP9(0) TP9(0)/pin_input TP9(0)/pad_out 14.510
Route 1 TP9(0)_PAD TP9(0)/pad_out TP9(0)_PAD 0.000
Clock Clock path delay 0.000
Net_31/q TP9(0)_PAD 25.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 Net_31 Input Delay Net_31/q 0.000
Route 1 Net_31 Net_31/q TP9(0)/pin_input 11.313
iocell2 P6[5] 1 TP9(0) TP9(0)/pin_input TP9(0)/pad_out 14.510
Route 1 TP9(0)_PAD TP9(0)/pad_out TP9(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 100ns
Affects clock : Clock_1
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_32/q \SPIS_1:BSPIS:BitCounter\/reset -1.886 101.886
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:BitCounter\/reset 3.588
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ RECOVERY -0.000
Clock Skew -6.724
+ Removal
Source Destination Slack (ns) Violation
Net_32/q \SPIS_1:BSPIS:BitCounter\/reset -1.886 REMOVAL
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 Net_32 Net_32/clock_0 Net_32/q 1.250
Route 1 Net_32 Net_32/q \SPIS_1:BSPIS:BitCounter\/reset 3.588
count7cell U(3,1) 1 \SPIS_1:BSPIS:BitCounter\ REMOVAL 0.000
Clock Skew -6.724