Static Timing Analysis

Project : SPI_Design01
Build Time : 11/09/16 12:29:34
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock CyMASTER_CLK 2.000 MHz 2.000 MHz 55.435 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
s_sclk_pin(0)_PAD s_sclk_pin(0)_PAD UNKNOWN UNKNOWN 35.704 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 55.435 MHz 18.039 481.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 6.254
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.645
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:TxStsReg\/status_3 61.569 MHz 16.242 483.758
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:load_rx_data\/main_0 6.254
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_0 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:TxStsReg\/status_3 4.198
statusicell3 U(2,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:RxStsReg\/status_6 62.267 MHz 16.060 483.940
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM:BSPIM:count_4\ \SPIM:BSPIM:BitCounter\/count_4 \SPIM:BSPIM:rx_status_6\/main_0 8.009
macrocell13 U(3,0) 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/main_0 \SPIM:BSPIM:rx_status_6\/q 3.350
Route 1 \SPIM:BSPIM:rx_status_6\ \SPIM:BSPIM:rx_status_6\/q \SPIM:BSPIM:RxStsReg\/status_6 2.261
statusicell4 U(2,0) 1 \SPIM:BSPIM:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_1\/q \SPIM:BSPIM:TxStsReg\/status_0 65.820 MHz 15.193 484.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell20 U(3,1) 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/clock_0 \SPIM:BSPIM:state_1\/q 1.250
Route 1 \SPIM:BSPIM:state_1\ \SPIM:BSPIM:state_1\/q \SPIM:BSPIM:tx_status_0\/main_1 4.520
macrocell11 U(3,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_1 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 5.573
statusicell3 U(2,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:state_0\/q \SPIM:BSPIM:TxStsReg\/status_0 66.317 MHz 15.079 484.921
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,1) 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/clock_0 \SPIM:BSPIM:state_0\/q 1.250
Route 1 \SPIM:BSPIM:state_0\ \SPIM:BSPIM:state_0\/q \SPIM:BSPIM:tx_status_0\/main_2 4.406
macrocell11 U(3,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_2 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 5.573
statusicell3 U(2,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 68.428 MHz 14.614 485.386
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:load_rx_data\/main_4 2.829
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_4 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.645
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 68.601 MHz 14.577 485.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM:BSPIM:count_2\ \SPIM:BSPIM:BitCounter\/count_2 \SPIM:BSPIM:load_rx_data\/main_2 2.792
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_2 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.645
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 69.295 MHz 14.431 485.569
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:load_rx_data\/main_1 2.646
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_1 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.645
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:sR8:Dp:u0\/f1_load 69.435 MHz 14.402 485.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:load_rx_data\/main_3 2.617
macrocell10 U(3,1) 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/main_3 \SPIM:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM:BSPIM:load_rx_data\ \SPIM:BSPIM:load_rx_data\/q \SPIM:BSPIM:sR8:Dp:u0\/f1_load 3.645
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\SPIM:BSPIM:state_2\/q \SPIM:BSPIM:TxStsReg\/status_0 70.517 MHz 14.181 485.819
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/clock_0 \SPIM:BSPIM:state_2\/q 1.250
Route 1 \SPIM:BSPIM:state_2\ \SPIM:BSPIM:state_2\/q \SPIM:BSPIM:tx_status_0\/main_0 3.508
macrocell11 U(3,1) 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/main_0 \SPIM:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM:BSPIM:tx_status_0\ \SPIM:BSPIM:tx_status_0\/q \SPIM:BSPIM:TxStsReg\/status_0 5.573
statusicell3 U(2,1) 1 \SPIM:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 71.408 MHz 14.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,0) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.220
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 1.619
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 72.860 MHz 13.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 4.516
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 75.449 MHz 13.254
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 4.045
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 75.557 MHz 13.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 4.026
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 76.453 MHz 13.080
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.871
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew 1.619
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 54.930 MHz 18.205
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 4.516
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 56.389 MHz 17.734
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 4.045
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 56.449 MHz 17.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 4.026
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 56.948 MHz 17.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.871
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 66.596 MHz 15.016
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 2.542
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 66.653 MHz 15.003
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 2.529
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 67.852 MHz 14.738
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 2.264
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 67.958 MHz 14.715
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 2.241
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew 1.619
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 3.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.350
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.817
macrocell15 U(2,3) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_2\/main_6 2.607
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 \SPIM:BSPIM:state_1\/main_6 2.607
macrocell20 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_1 Net_30/main_8 3.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM:BSPIM:count_1\ \SPIM:BSPIM:BitCounter\/count_1 Net_30/main_8 2.617
macrocell18 U(3,1) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 3.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_2\/main_4 2.638
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_1\/main_4 3.258
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 \SPIM:BSPIM:state_1\/main_4 2.638
macrocell20 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_3 Net_30/main_6 3.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_3 0.620
Route 1 \SPIM:BSPIM:count_3\ \SPIM:BSPIM:BitCounter\/count_3 Net_30/main_6 2.646
macrocell18 U(3,1) 1 Net_30 HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 3.309
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.959
macrocell14 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_2\/main_7 3.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_2\/main_7 2.788
macrocell19 U(3,1) 1 \SPIM:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_1\/main_7 3.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,1) 1 \SPIM:BSPIM:BitCounter\ \SPIM:BSPIM:BitCounter\/clock \SPIM:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM:BSPIM:count_0\ \SPIM:BSPIM:BitCounter\/count_0 \SPIM:BSPIM:state_1\/main_7 2.788
macrocell20 U(3,1) 1 \SPIM:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 5010.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(3,0) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.220
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 1.619
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5008.370
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.871
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5008.525
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 4.026
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5008.544
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 4.045
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5009.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 4.516
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew 1.619
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 9.855
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 2.241
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 9.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 2.264
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 10.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 2.529
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 10.156
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 2.542
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 11.760
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 3.871
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 11.915
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 4.026
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 11.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 4.045
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 1.619
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 12.405
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,0) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 4.516
macrocell2 U(3,2) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 2.300
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew 1.619
+ Input To Output Section
Source Destination Delay (ns)
s_ss_pin(0)_PAD s_miso_pin(0)_PAD 38.683
Type Location Fanout Instance/Net Source Dest Delay (ns)
SPI_Design01 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)_PAD 0.000
Route 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)/pad_in 0.000
iocell6 P0[7] 1 s_ss_pin(0) s_ss_pin(0)/pad_in s_ss_pin(0)/fb 7.644
Route 1 Net_109 s_ss_pin(0)/fb Net_37/main_0 5.292
macrocell5 U(3,3) 1 Net_37 Net_37/main_0 Net_37/q 3.350
Route 1 Net_37 Net_37/q s_miso_pin(0)/pin_input 6.653
iocell7 P0[3] 1 s_miso_pin(0) s_miso_pin(0)/pin_input s_miso_pin(0)/pad_out 15.744
Route 1 s_miso_pin(0)_PAD s_miso_pin(0)/pad_out s_miso_pin(0)_PAD 0.000
+ Input To Clock Section
+ Clock
Source Destination Delay (ns)
m_miso_pin(0)_PAD \SPIM:BSPIM:sR8:Dp:u0\/route_si 18.198
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 m_miso_pin(0)_PAD m_miso_pin(0)_PAD m_miso_pin(0)/pad_in 0.000
iocell1 P0[2] 1 m_miso_pin(0) m_miso_pin(0)/pad_in m_miso_pin(0)/fb 7.950
Route 1 Net_20 m_miso_pin(0)/fb \SPIM:BSPIM:sR8:Dp:u0\/route_si 6.748
datapathcell2 U(2,1) 1 \SPIM:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ s_sclk_pin(0)_PAD
Source Destination Delay (ns)
s_ss_pin(0)_PAD \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_2 15.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)/pad_in 0.000
iocell6 P0[7] 1 s_ss_pin(0) s_ss_pin(0)/pad_in s_ss_pin(0)/fb 7.644
Route 1 Net_109 s_ss_pin(0)/fb \SPIS:BSPIS:inv_ss\/main_0 8.708
macrocell1 U(3,0) 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/main_0 \SPIS:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_2 5.084
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Clock path delay -14.229
s_mosi_pin(0)_PAD \SPIS:BSPIS:sR8:Dp:u0\/route_si 10.745
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_mosi_pin(0)_PAD s_mosi_pin(0)_PAD s_mosi_pin(0)/pad_in 0.000
iocell4 P0[1] 1 s_mosi_pin(0) s_mosi_pin(0)/pad_in s_mosi_pin(0)/fb 7.962
Route 1 Net_33 s_mosi_pin(0)/fb \SPIS:BSPIS:mosi_to_dp\/main_5 8.097
macrocell9 U(3,0) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_5 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 3.595
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Clock path delay -14.229
s_mosi_pin(0)_PAD \SPIS:BSPIS:mosi_tmp\/main_0 3.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_mosi_pin(0)_PAD s_mosi_pin(0)_PAD s_mosi_pin(0)/pad_in 0.000
iocell4 P0[1] 1 s_mosi_pin(0) s_mosi_pin(0)/pad_in s_mosi_pin(0)/fb 7.962
Route 1 Net_33 s_mosi_pin(0)/fb \SPIS:BSPIS:mosi_tmp\/main_0 8.097
macrocell16 U(3,0) 1 \SPIS:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -15.848
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
Net_31/q m_sclk_pin(0)_PAD 23.946
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,0) 1 Net_31 Net_31/clock_0 Net_31/q 1.250
Route 1 Net_31 Net_31/q m_sclk_pin(0)/pin_input 7.816
iocell3 P0[4] 1 m_sclk_pin(0) m_sclk_pin(0)/pin_input m_sclk_pin(0)/pad_out 14.880
Route 1 m_sclk_pin(0)_PAD m_sclk_pin(0)/pad_out m_sclk_pin(0)_PAD 0.000
Clock Clock path delay 0.000
Net_30/q m_mosi_pin(0)_PAD 23.638
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,1) 1 Net_30 Net_30/clock_0 Net_30/q 1.250
Route 1 Net_30 Net_30/q m_mosi_pin(0)/pin_input 7.137
iocell2 P0[0] 1 m_mosi_pin(0) m_mosi_pin(0)/pin_input m_mosi_pin(0)/pad_out 15.251
Route 1 m_mosi_pin(0)_PAD m_mosi_pin(0)/pad_out m_mosi_pin(0)_PAD 0.000
Clock Clock path delay 0.000
Net_107/q m_ss_pin(0)_PAD 22.980
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,3) 1 Net_107 Net_107/clock_0 Net_107/q 1.250
Route 1 Net_107 Net_107/q m_ss_pin(0)/pin_input 6.169
iocell15 P0[6] 1 m_ss_pin(0) m_ss_pin(0)/pin_input m_ss_pin(0)/pad_out 15.561
Route 1 m_ss_pin(0)_PAD m_ss_pin(0)/pad_out m_ss_pin(0)_PAD 0.000
Clock Clock path delay 0.000
+ s_sclk_pin(0)_PAD
Source Destination Delay (ns)
\SPIS:BSPIS:sR8:Dp:u0\/so_comb s_miso_pin(0)_PAD 52.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,2) 1 \SPIS:BSPIS:sR8:Dp:u0\ \SPIS:BSPIS:sR8:Dp:u0\/clock \SPIS:BSPIS:sR8:Dp:u0\/so_comb 9.160
Route 1 \SPIS:BSPIS:miso_from_dp\ \SPIS:BSPIS:sR8:Dp:u0\/so_comb Net_37/main_1 2.882
macrocell5 U(3,3) 1 Net_37 Net_37/main_1 Net_37/q 3.350
Route 1 Net_37 Net_37/q s_miso_pin(0)/pin_input 6.653
iocell7 P0[3] 1 s_miso_pin(0) s_miso_pin(0)/pin_input s_miso_pin(0)/pad_out 15.744
Route 1 s_miso_pin(0)_PAD s_miso_pin(0)/pad_out s_miso_pin(0)_PAD 0.000
Clock Clock path delay 14.229