Static Timing Analysis

Project : Filter_ADC_VDAC01
Build Time : 11/03/15 11:00:44
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
Note: If your design will only ever run at typical room temperatures, selecting the narrower temperature range in the system DWR for your application helps the tool to find timing-compliant routing solutions.
Violation Source Clock Destination Clock Slack(ns)
Async
\ADC_DelSig:DSM\/dec_clock CyBUS_CLK
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_DelSig_Ext_CP_Clk ADC_DelSig_Ext_CP_Clk 70.000 MHz 70.000 MHz N/A
ADC_DelSig_Ext_CP_Clk(routed) ADC_DelSig_Ext_CP_Clk(routed) 70.000 MHz 70.000 MHz N/A
ADC_DelSig_theACLK(fixed-function) ADC_DelSig_theACLK(fixed-function) 1.207 MHz 1.207 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 70.000 MHz 70.000 MHz N/A
ADC_DelSig_theACLK CyMASTER_CLK 1.207 MHz 1.207 MHz N/A
CyBUS_CLK CyMASTER_CLK 70.000 MHz 70.000 MHz N/A
CyPLL_OUT CyPLL_OUT 70.000 MHz 70.000 MHz N/A
\ADC_DelSig:DSM\/dec_clock \ADC_DelSig:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Asynchronous Clock Crossing Section
+ Source Clock \ADC_DelSig:DSM\/dec_clock
Source Destination Delay (ns)
\ADC_DelSig:DEC\/interrupt DMA_1/dmareq 12.267
Type Location Fanout Instance/Net Source Dest Delay (ns)
decimatorcell F(Decimator,0) 1 \ADC_DelSig:DEC\ \ADC_DelSig:DEC\/aclock \ADC_DelSig:DEC\/interrupt 1.000
Route 1 Net_158 \ADC_DelSig:DEC\/interrupt DMA_1/dmareq 4.167
drqcell2 [DrqHod=(0)][DrqId=(0)] 1 DMA_1 SETUP 7.100
Clock Skew 0.000