Static Timing Analysis

Project : CharLCD05
Build Time : 07/29/19 13:29:16
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/dclk_glb_ff_0 ClockBlock/dclk_glb_ff_0 UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 31.509 MHz
CLK10 CyMASTER_CLK 34.483  Hz 34.483  Hz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\FreqDiv_1:count_11\/q Net_617/main_1 31.509 MHz 31.737 9.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,4) 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/clock_0 \FreqDiv_1:count_11\/q 1.250
Route 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/q \FreqDiv_1:CUBEtmp0_split\/main_11 7.642
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_11 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_2/main_9 3.387
macrocell12 U(2,0) 1 Net_617_split_2 Net_617_split_2/main_9 Net_617_split_2/q 3.350
Route 1 Net_617_split_2 Net_617_split_2/q Net_617/main_1 3.598
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_11\/q Net_617/main_3 31.521 MHz 31.725 9.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,4) 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/clock_0 \FreqDiv_1:count_11\/q 1.250
Route 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/q \FreqDiv_1:CUBEtmp0_split\/main_11 7.642
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_11 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_4/main_9 3.382
macrocell10 U(3,0) 1 Net_617_split_4 Net_617_split_4/main_9 Net_617_split_4/q 3.350
Route 1 Net_617_split_4 Net_617_split_4/q Net_617/main_3 3.591
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_11\/q Net_617/main_2 31.644 MHz 31.602 10.065
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,4) 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/clock_0 \FreqDiv_1:count_11\/q 1.250
Route 1 \FreqDiv_1:count_11\ \FreqDiv_1:count_11\/q \FreqDiv_1:CUBEtmp0_split\/main_11 7.642
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_11 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_3/main_9 3.950
macrocell11 U(2,3) 1 Net_617_split_3 Net_617_split_3/main_9 Net_617_split_3/q 3.350
Route 1 Net_617_split_3 Net_617_split_3/q Net_617/main_2 2.900
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_12\/q Net_617/main_1 32.317 MHz 30.943 10.724
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,4) 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/clock_0 \FreqDiv_1:count_12\/q 1.250
Route 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/q \FreqDiv_1:CUBEtmp0_split\/main_10 6.848
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_10 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_2/main_9 3.387
macrocell12 U(2,0) 1 Net_617_split_2 Net_617_split_2/main_9 Net_617_split_2/q 3.350
Route 1 Net_617_split_2 Net_617_split_2/q Net_617/main_1 3.598
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_12\/q Net_617/main_3 32.330 MHz 30.931 10.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,4) 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/clock_0 \FreqDiv_1:count_12\/q 1.250
Route 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/q \FreqDiv_1:CUBEtmp0_split\/main_10 6.848
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_10 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_4/main_9 3.382
macrocell10 U(3,0) 1 Net_617_split_4 Net_617_split_4/main_9 Net_617_split_4/q 3.350
Route 1 Net_617_split_4 Net_617_split_4/q Net_617/main_3 3.591
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_12\/q Net_617/main_2 32.459 MHz 30.808 10.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,4) 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/clock_0 \FreqDiv_1:count_12\/q 1.250
Route 1 \FreqDiv_1:count_12\ \FreqDiv_1:count_12\/q \FreqDiv_1:CUBEtmp0_split\/main_10 6.848
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_10 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_3/main_9 3.950
macrocell11 U(2,3) 1 Net_617_split_3 Net_617_split_3/main_9 Net_617_split_3/q 3.350
Route 1 Net_617_split_3 Net_617_split_3/q Net_617/main_2 2.900
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_18\/q Net_617/main_1 34.039 MHz 29.378 12.289
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,2) 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/clock_0 \FreqDiv_1:count_18\/q 1.250
Route 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/q \FreqDiv_1:CUBEtmp0_split\/main_4 5.283
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_4 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_2/main_9 3.387
macrocell12 U(2,0) 1 Net_617_split_2 Net_617_split_2/main_9 Net_617_split_2/q 3.350
Route 1 Net_617_split_2 Net_617_split_2/q Net_617/main_1 3.598
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_18\/q Net_617/main_3 34.053 MHz 29.366 12.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,2) 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/clock_0 \FreqDiv_1:count_18\/q 1.250
Route 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/q \FreqDiv_1:CUBEtmp0_split\/main_4 5.283
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_4 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_4/main_9 3.382
macrocell10 U(3,0) 1 Net_617_split_4 Net_617_split_4/main_9 Net_617_split_4/q 3.350
Route 1 Net_617_split_4 Net_617_split_4/q Net_617/main_3 3.591
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_18\/q Net_617/main_2 34.196 MHz 29.243 12.424
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(3,2) 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/clock_0 \FreqDiv_1:count_18\/q 1.250
Route 1 \FreqDiv_1:count_18\ \FreqDiv_1:count_18\/q \FreqDiv_1:CUBEtmp0_split\/main_4 5.283
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_4 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_3/main_9 3.950
macrocell11 U(2,3) 1 Net_617_split_3 Net_617_split_3/main_9 Net_617_split_3/q 3.350
Route 1 Net_617_split_3 Net_617_split_3/q Net_617/main_2 2.900
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
\FreqDiv_1:count_16\/q Net_617/main_1 34.228 MHz 29.216 12.451
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,3) 1 \FreqDiv_1:count_16\ \FreqDiv_1:count_16\/clock_0 \FreqDiv_1:count_16\/q 1.250
Route 1 \FreqDiv_1:count_16\ \FreqDiv_1:count_16\/q \FreqDiv_1:CUBEtmp0_split\/main_6 5.121
macrocell1 U(3,1) 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/main_6 \FreqDiv_1:CUBEtmp0_split\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0_split\ \FreqDiv_1:CUBEtmp0_split\/q \FreqDiv_1:CUBEtmp0\/main_11 2.300
macrocell2 U(2,1) 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/main_11 \FreqDiv_1:CUBEtmp0\/q 3.350
Route 1 \FreqDiv_1:CUBEtmp0\ \FreqDiv_1:CUBEtmp0\/q Net_617_split_2/main_9 3.387
macrocell12 U(2,0) 1 Net_617_split_2 Net_617_split_2/main_9 Net_617_split_2/q 3.350
Route 1 Net_617_split_2 Net_617_split_2/q Net_617/main_1 3.598
macrocell21 U(2,2) 1 Net_617 SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\FreqDiv_1:count_22\/q \FreqDiv_1:count_22\/main_1 3.481
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(3,0) 1 \FreqDiv_1:count_22\ \FreqDiv_1:count_22\/clock_0 \FreqDiv_1:count_22\/q 1.250
macrocell27 U(3,0) 1 \FreqDiv_1:count_22\ \FreqDiv_1:count_22\/q \FreqDiv_1:count_22\/main_1 2.231
macrocell27 U(3,0) 1 \FreqDiv_1:count_22\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_2\/q \FreqDiv_1:count_2\/main_1 3.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(2,0) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/clock_0 \FreqDiv_1:count_2\/q 1.250
macrocell47 U(2,0) 1 \FreqDiv_1:count_2\ \FreqDiv_1:count_2\/q \FreqDiv_1:count_2\/main_1 2.252
macrocell47 U(2,0) 1 \FreqDiv_1:count_2\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_7\/q \FreqDiv_1:count_7\/main_1 3.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(3,4) 1 \FreqDiv_1:count_7\ \FreqDiv_1:count_7\/clock_0 \FreqDiv_1:count_7\/q 1.250
macrocell42 U(3,4) 1 \FreqDiv_1:count_7\ \FreqDiv_1:count_7\/q \FreqDiv_1:count_7\/main_1 2.295
macrocell42 U(3,4) 1 \FreqDiv_1:count_7\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_19\/q \FreqDiv_1:count_20\/main_2 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,2) 1 \FreqDiv_1:count_19\ \FreqDiv_1:count_19\/clock_0 \FreqDiv_1:count_19\/q 1.250
Route 1 \FreqDiv_1:count_19\ \FreqDiv_1:count_19\/q \FreqDiv_1:count_20\/main_2 2.581
macrocell29 U(3,2) 1 \FreqDiv_1:count_20\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_19\/q \FreqDiv_1:count_19\/main_1 3.831
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(3,2) 1 \FreqDiv_1:count_19\ \FreqDiv_1:count_19\/clock_0 \FreqDiv_1:count_19\/q 1.250
macrocell30 U(3,2) 1 \FreqDiv_1:count_19\ \FreqDiv_1:count_19\/q \FreqDiv_1:count_19\/main_1 2.581
macrocell30 U(3,2) 1 \FreqDiv_1:count_19\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_17\/q \FreqDiv_1:count_20\/main_4 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/clock_0 \FreqDiv_1:count_17\/q 1.250
Route 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/q \FreqDiv_1:count_20\/main_4 2.584
macrocell29 U(3,2) 1 \FreqDiv_1:count_20\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_17\/q \FreqDiv_1:count_19\/main_3 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/clock_0 \FreqDiv_1:count_17\/q 1.250
Route 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/q \FreqDiv_1:count_19\/main_3 2.584
macrocell30 U(3,2) 1 \FreqDiv_1:count_19\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_17\/q \FreqDiv_1:count_18\/main_2 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/clock_0 \FreqDiv_1:count_17\/q 1.250
Route 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/q \FreqDiv_1:count_18\/main_2 2.584
macrocell31 U(3,2) 1 \FreqDiv_1:count_18\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_17\/q \FreqDiv_1:count_17\/main_1 3.834
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/clock_0 \FreqDiv_1:count_17\/q 1.250
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ \FreqDiv_1:count_17\/q \FreqDiv_1:count_17\/main_1 2.584
macrocell32 U(3,2) 1 \FreqDiv_1:count_17\ HOLD 0.000
Clock Skew 0.000
\FreqDiv_1:count_8\/q \FreqDiv_1:count_14\/main_7 3.858
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell41 U(2,4) 1 \FreqDiv_1:count_8\ \FreqDiv_1:count_8\/clock_0 \FreqDiv_1:count_8\/q 1.250
Route 1 \FreqDiv_1:count_8\ \FreqDiv_1:count_8\/q \FreqDiv_1:count_14\/main_7 2.608
macrocell35 U(2,4) 1 \FreqDiv_1:count_14\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ CyBUS_CLK
Source Destination Delay (ns)
SwIn(1)_PAD SwOutData_1/main_0 18.776
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SwIn(1)_PAD SwIn(1)_PAD SwIn(1)/pad_in 0.000
iocell13 P0[1] 1 SwIn(1) SwIn(1)/pad_in SwIn(1)/fb 7.962
Route 1 SwInData_1 SwIn(1)/fb SwOutData_1/main_0 7.304
macrocell23 U(3,1) 1 SwOutData_1 SETUP 3.510
Clock Clock path delay 0.000
SwIn(3)_PAD SwOutData_3/main_0 17.403
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SwIn(3)_PAD SwIn(3)_PAD SwIn(3)/pad_in 0.000
iocell15 P0[3] 1 SwIn(3) SwIn(3)/pad_in SwIn(3)/fb 7.958
Route 1 SwInData_3 SwIn(3)/fb SwOutData_3/main_0 5.935
macrocell25 U(3,3) 1 SwOutData_3 SETUP 3.510
Clock Clock path delay 0.000
SwIn(2)_PAD SwOutData_2/main_0 17.047
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SwIn(2)_PAD SwIn(2)_PAD SwIn(2)/pad_in 0.000
iocell14 P0[2] 1 SwIn(2) SwIn(2)/pad_in SwIn(2)/fb 7.950
Route 1 SwInData_2 SwIn(2)/fb SwOutData_2/main_0 5.587
macrocell24 U(3,4) 1 SwOutData_2 SETUP 3.510
Clock Clock path delay 0.000
SwIn(0)_PAD SwOutData_0/main_0 16.161
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SwIn(0)_PAD SwIn(0)_PAD SwIn(0)/pad_in 0.000
iocell12 P0[0] 1 SwIn(0) SwIn(0)/pad_in SwIn(0)/fb 7.922
Route 1 SwInData_0 SwIn(0)/fb SwOutData_0/main_0 4.729
macrocell22 U(3,4) 1 SwOutData_0 SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
SwOutData_0/q SwOut(0)_PAD 31.588
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,4) 1 SwOutData_0 SwOutData_0/clock_0 SwOutData_0/q 1.250
Route 1 SwOutData_0 SwOutData_0/q NotData_0/main_0 2.297
macrocell19 U(3,4) 1 NotData_0 NotData_0/main_0 NotData_0/q 3.350
Route 1 NotData_0 NotData_0/q SwOut(0)/pin_input 8.836
iocell16 P12[0] 1 SwOut(0) SwOut(0)/pin_input SwOut(0)/pad_out 15.855
Route 1 SwOut(0)_PAD SwOut(0)/pad_out SwOut(0)_PAD 0.000
Clock Clock path delay 0.000
SwOutData_1/q SwOut(1)_PAD 29.440
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(3,1) 1 SwOutData_1 SwOutData_1/clock_0 SwOutData_1/q 1.250
Route 1 SwOutData_1 SwOutData_1/q NotData_1/main_0 2.301
macrocell18 U(3,1) 1 NotData_1 NotData_1/main_0 NotData_1/q 3.350
Route 1 NotData_1 NotData_1/q SwOut(1)/pin_input 6.606
iocell17 P12[1] 1 SwOut(1) SwOut(1)/pin_input SwOut(1)/pad_out 15.933
Route 1 SwOut(1)_PAD SwOut(1)/pad_out SwOut(1)_PAD 0.000
Clock Clock path delay 0.000
SwOutData_3/q SwOut(3)_PAD 28.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(3,3) 1 SwOutData_3 SwOutData_3/clock_0 SwOutData_3/q 1.250
Route 1 SwOutData_3 SwOutData_3/q NotData_3/main_0 2.292
macrocell16 U(3,3) 1 NotData_3 NotData_3/main_0 NotData_3/q 3.350
Route 1 NotData_3 NotData_3/q SwOut(3)/pin_input 5.462
iocell19 P12[3] 1 SwOut(3) SwOut(3)/pin_input SwOut(3)/pad_out 16.196
Route 1 SwOut(3)_PAD SwOut(3)/pad_out SwOut(3)_PAD 0.000
Clock Clock path delay 0.000
SwOutData_2/q SwOut(2)_PAD 28.471
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(3,4) 1 SwOutData_2 SwOutData_2/clock_0 SwOutData_2/q 1.250
Route 1 SwOutData_2 SwOutData_2/q NotData_2/main_0 2.311
macrocell17 U(3,4) 1 NotData_2 NotData_2/main_0 NotData_2/q 3.350
Route 1 NotData_2 NotData_2/q SwOut(2)/pin_input 5.894
iocell18 P12[2] 1 SwOut(2) SwOut(2)/pin_input SwOut(2)/pad_out 15.666
Route 1 SwOut(2)_PAD SwOut(2)/pad_out SwOut(2)_PAD 0.000
Clock Clock path delay 0.000