Static Timing Analysis

Project : micro sd card test
Build Time : 12/23/22 09:36:38
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus_glb_ff ClockBlock/clk_bus_glb_ff UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 6.000 MHz 6.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 6.000 MHz 6.000 MHz N/A
emFile_Clock_1 CyMASTER_CLK 6.000 MHz 6.000 MHz 55.411 MHz
CyPLL_OUT CyPLL_OUT 48.000 MHz 48.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 166.667ns(6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 55.411 MHz 18.047 148.620
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 3.520
macrocell7 U(2,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_3 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.307
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 55.919 MHz 17.883 148.784
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/clock \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb 5.360
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/so_comb \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_3 3.376
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_3 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 65.915 MHz 15.171 151.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_0 1.940
Route 1 \emFile:SPI0:BSPIM:count_0\ \emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:load_rx_data\/main_4 3.794
macrocell2 U(2,4) 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/main_4 \emFile:SPI0:BSPIM:load_rx_data\/q 3.350
Route 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/q \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 3.237
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 65.941 MHz 15.165 151.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_4 1.940
Route 1 \emFile:SPI0:BSPIM:count_4\ \emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:load_rx_data\/main_0 3.788
macrocell2 U(2,4) 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/main_0 \emFile:SPI0:BSPIM:load_rx_data\/q 3.350
Route 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/q \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 3.237
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 66.631 MHz 15.008 151.659
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_3 1.940
Route 1 \emFile:SPI0:BSPIM:count_3\ \emFile:SPI0:BSPIM:BitCounter\/count_3 \emFile:SPI0:BSPIM:load_rx_data\/main_1 3.631
macrocell2 U(2,4) 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/main_1 \emFile:SPI0:BSPIM:load_rx_data\/q 3.350
Route 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/q \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 3.237
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 67.119 MHz 14.899 151.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_0 1.940
Route 1 \emFile:SPI0:BSPIM:count_0\ \emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_7 3.792
macrocell7 U(2,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_7 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.307
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 67.150 MHz 14.892 151.775
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_4 1.940
Route 1 \emFile:SPI0:BSPIM:count_4\ \emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_4 3.785
macrocell7 U(2,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/main_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\ \emFile:SPI0:BSPIM:mosi_pre_reg_split_1\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_1 2.307
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 67.204 MHz 14.880 151.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_0 1.940
Route 1 \emFile:SPI0:BSPIM:count_0\ \emFile:SPI0:BSPIM:BitCounter\/count_0 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_8 3.793
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_8 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 67.331 MHz 14.852 151.815
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_4 1.940
Route 1 \emFile:SPI0:BSPIM:count_4\ \emFile:SPI0:BSPIM:BitCounter\/count_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_4 3.765
macrocell1 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/main_4 \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q 3.350
Route 1 \emFile:SPI0:BSPIM:mosi_pre_reg_split\ \emFile:SPI0:BSPIM:mosi_pre_reg_split\/q \emFile:SPI0:BSPIM:mosi_pre_reg\/main_0 2.287
macrocell13 U(3,4) 1 \emFile:SPI0:BSPIM:mosi_pre_reg\ SETUP 3.510
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 68.190 MHz 14.665 152.002
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_2 1.940
Route 1 \emFile:SPI0:BSPIM:count_2\ \emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:load_rx_data\/main_2 3.288
macrocell2 U(2,4) 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/main_2 \emFile:SPI0:BSPIM:load_rx_data\/q 3.350
Route 1 \emFile:SPI0:BSPIM:load_rx_data\ \emFile:SPI0:BSPIM:load_rx_data\/q \emFile:SPI0:BSPIM:sR8:Dp:u0\/f1_load 3.237
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 2.850
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\emFile:SPI0:BSPIM:load_cond\/q \emFile:SPI0:BSPIM:load_cond\/main_8 3.549
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(3,3) 1 \emFile:SPI0:BSPIM:load_cond\ \emFile:SPI0:BSPIM:load_cond\/clock_0 \emFile:SPI0:BSPIM:load_cond\/q 1.250
macrocell14 U(3,3) 1 \emFile:SPI0:BSPIM:load_cond\ \emFile:SPI0:BSPIM:load_cond\/q \emFile:SPI0:BSPIM:load_cond\/main_8 2.299
macrocell14 U(3,3) 1 \emFile:SPI0:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:mosi_hs_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_4 3.556
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ \emFile:SPI0:BSPIM:mosi_hs_reg\/clock_0 \emFile:SPI0:BSPIM:mosi_hs_reg\/q 1.250
macrocell12 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ \emFile:SPI0:BSPIM:mosi_hs_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_4 2.306
macrocell12 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_5 3.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_from_dp_reg\ \emFile:SPI0:BSPIM:mosi_from_dp_reg\/clock_0 \emFile:SPI0:BSPIM:mosi_from_dp_reg\/q 1.250
Route 1 \emFile:SPI0:BSPIM:mosi_from_dp_reg\ \emFile:SPI0:BSPIM:mosi_from_dp_reg\/q \emFile:SPI0:BSPIM:mosi_hs_reg\/main_5 2.311
macrocell12 U(3,3) 1 \emFile:SPI0:BSPIM:mosi_hs_reg\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_1\/main_6 3.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_1 0.620
Route 1 \emFile:SPI0:BSPIM:count_1\ \emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_1\/main_6 2.964
macrocell9 U(3,4) 1 \emFile:SPI0:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_0\/main_6 3.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_1 0.620
Route 1 \emFile:SPI0:BSPIM:count_1\ \emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_0\/main_6 2.964
macrocell10 U(3,4) 1 \emFile:SPI0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_2\/main_6 3.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_1 0.620
Route 1 \emFile:SPI0:BSPIM:count_1\ \emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:state_2\/main_6 3.110
macrocell8 U(2,4) 1 \emFile:SPI0:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:ld_ident\/main_6 3.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_1 0.620
Route 1 \emFile:SPI0:BSPIM:count_1\ \emFile:SPI0:BSPIM:BitCounter\/count_1 \emFile:SPI0:BSPIM:ld_ident\/main_6 3.110
macrocell16 U(2,4) 1 \emFile:SPI0:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:cnt_enable\/q \emFile:SPI0:BSPIM:cnt_enable\/main_3 3.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(2,3) 1 \emFile:SPI0:BSPIM:cnt_enable\ \emFile:SPI0:BSPIM:cnt_enable\/clock_0 \emFile:SPI0:BSPIM:cnt_enable\/q 1.250
macrocell17 U(2,3) 1 \emFile:SPI0:BSPIM:cnt_enable\ \emFile:SPI0:BSPIM:cnt_enable\/q \emFile:SPI0:BSPIM:cnt_enable\/main_3 2.630
macrocell17 U(2,3) 1 \emFile:SPI0:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_1\/main_5 3.886
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_2 0.620
Route 1 \emFile:SPI0:BSPIM:count_2\ \emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_1\/main_5 3.266
macrocell9 U(3,4) 1 \emFile:SPI0:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_0\/main_5 3.886
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,4) 1 \emFile:SPI0:BSPIM:BitCounter\ \emFile:SPI0:BSPIM:BitCounter\/clock \emFile:SPI0:BSPIM:BitCounter\/count_2 0.620
Route 1 \emFile:SPI0:BSPIM:count_2\ \emFile:SPI0:BSPIM:BitCounter\/count_2 \emFile:SPI0:BSPIM:state_0\/main_5 3.266
macrocell10 U(3,4) 1 \emFile:SPI0:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ emFile_Clock_1
Source Destination Delay (ns)
\emFile:miso0(0)_PAD\ \emFile:SPI0:BSPIM:sR8:Dp:u0\/route_si 15.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 \emFile:miso0(0)_PAD\ \emFile:miso0(0)_PAD\ \emFile:miso0(0)\/pad_in 0.000
iocell2 P12[2] 1 \emFile:miso0(0)\ \emFile:miso0(0)\/pad_in \emFile:miso0(0)\/fb 7.315
Route 1 \emFile:Net_16\ \emFile:miso0(0)\/fb \emFile:SPI0:BSPIM:sR8:Dp:u0\/route_si 4.757
datapathcell1 U(2,3) 1 \emFile:SPI0:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ ClockBlock/clk_bus_glb_ff
Source Destination Delay (ns)
\I2COLED:I2C_FF\/sda_out sda(0)_PAD:out 24.477
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2COLED:I2C_FF\ \I2COLED:I2C_FF\/clock \I2COLED:I2C_FF\/sda_out 1.000
Route 1 \I2COLED:sda_x_wire\ \I2COLED:I2C_FF\/sda_out sda(0)/pin_input 7.544
iocell5 P12[1] 1 sda(0) sda(0)/pin_input sda(0)/pad_out 15.933
Route 1 sda(0)_PAD sda(0)/pad_out sda(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2COLED:I2C_FF\/scl_out scl(0)_PAD:out 24.415
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2COLED:I2C_FF\ \I2COLED:I2C_FF\/clock \I2COLED:I2C_FF\/scl_out 1.000
Route 1 \I2COLED:Net_643_0\ \I2COLED:I2C_FF\/scl_out scl(0)/pin_input 7.560
iocell6 P12[0] 1 scl(0) scl(0)/pin_input scl(0)/pad_out 15.855
Route 1 scl(0)_PAD scl(0)/pad_out scl(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ emFile_Clock_1
Source Destination Delay (ns)
\emFile:SPI0:BSPIM:state_1\/q \emFile:mosi0(0)_PAD\ 31.127
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,4) 1 \emFile:SPI0:BSPIM:state_1\ \emFile:SPI0:BSPIM:state_1\/clock_0 \emFile:SPI0:BSPIM:state_1\/q 1.250
Route 1 \emFile:SPI0:BSPIM:state_1\ \emFile:SPI0:BSPIM:state_1\/q \emFile:Net_10\/main_1 4.815
macrocell3 U(3,3) 1 \emFile:Net_10\ \emFile:Net_10\/main_1 \emFile:Net_10\/q 3.350
Route 1 \emFile:Net_10\ \emFile:Net_10\/q \emFile:mosi0(0)\/pin_input 5.516
iocell1 P12[3] 1 \emFile:mosi0(0)\ \emFile:mosi0(0)\/pin_input \emFile:mosi0(0)\/pad_out 16.196
Route 1 \emFile:mosi0(0)_PAD\ \emFile:mosi0(0)\/pad_out \emFile:mosi0(0)_PAD\ 0.000
Clock Clock path delay 0.000
\emFile:Net_22\/q \emFile:sclk0(0)_PAD\ 25.705
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(2,4) 1 \emFile:Net_22\ \emFile:Net_22\/clock_0 \emFile:Net_22\/q 1.250
Route 1 \emFile:Net_22\ \emFile:Net_22\/q \emFile:sclk0(0)\/pin_input 7.840
iocell3 P12[4] 1 \emFile:sclk0(0)\ \emFile:sclk0(0)\/pin_input \emFile:sclk0(0)\/pad_out 16.615
Route 1 \emFile:sclk0(0)_PAD\ \emFile:sclk0(0)\/pad_out \emFile:sclk0(0)_PAD\ 0.000
Clock Clock path delay 0.000