Static Timing Analysis

Project : testing i2c with mpu6050 (13-11-21)
Build Time : 11/13/21 16:31:27
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus_glb_ff ClockBlock/clk_bus_glb_ff UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 63.621 MHz
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 56.870 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 63.621 MHz 15.718 25.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 4.927
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 89.310 MHz 11.197 30.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 5.944
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 89.413 MHz 11.184 30.483
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.931
macrocell24 U(0,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 98.232 MHz 10.180 31.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 4.927
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 98.232 MHz 10.180 31.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 4.927
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 98.309 MHz 10.172 31.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 4.919
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 98.309 MHz 10.172 31.495
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 4.919
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.870 MHz 17.584 13024.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.502
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 60.394 MHz 16.558 13025.109
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.639
macrocell3 U(0,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 5.489
statusicell1 U(0,1) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.861 MHz 16.431 13025.236
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,1) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.349
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 61.641 MHz 16.223 13025.444
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.008
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 62.661 MHz 15.959 13025.708
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,1) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.877
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:TxSts\/status_0 62.771 MHz 15.931 13025.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,1) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:tx_status_0\/main_1 5.342
macrocell3 U(0,1) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_1 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 5.489
statusicell1 U(0,1) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 63.488 MHz 15.751 13025.916
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.536
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 63.605 MHz 15.722 13025.945
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,1) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.507
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 64.234 MHz 15.568 13026.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.546
macrocell2 U(1,1) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.292
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 67.119 MHz 14.899 13026.768
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 2.684
macrocell5 U(0,0) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.255
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 6.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 4.919
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 6.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 4.919
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 4.927
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 6.670
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 4.927
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.674
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.931
macrocell24 U(0,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 7.687
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 5.944
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 12.248
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell4 P12[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 1.743
Route 1 Net_16 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 4.927
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.228
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,0) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.261
statusicell2 U(1,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 2.865
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_2\/main_8 2.245
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.875
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.255
macrocell19 U(1,0) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.978
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.788
macrocell12 U(1,1) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.801
macrocell9 U(1,1) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,1) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.801
macrocell10 U(1,1) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 3.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 2.526
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 3.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 2.548
macrocell18 U(0,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_1 3.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_1\/main_1 2.704
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_0\/main_1 3.324
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:pollcount_0\/main_1 2.704
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ ClockBlock/clk_bus_glb_ff
Source Destination Delay (ns)
\I2C:I2C_FF\/sda_out SDA(0)_PAD:out 24.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/sda_out 1.000
Route 1 \I2C:sda_x_wire\ \I2C:I2C_FF\/sda_out SDA(0)/pin_input 7.902
iocell1 P12[1] 1 SDA(0) SDA(0)/pin_input SDA(0)/pad_out 15.933
Route 1 SDA(0)_PAD SDA(0)/pad_out SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:I2C_FF\/scl_out SCL(0)_PAD:out 24.762
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/scl_out 1.000
Route 1 \I2C:Net_643_0\ \I2C:I2C_FF\/scl_out SCL(0)/pin_input 7.907
iocell2 P12[0] 1 SCL(0) SCL(0)/pin_input SCL(0)/pad_out 15.855
Route 1 SCL(0)_PAD SCL(0)/pad_out SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 30.400
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,1) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_20/main_0 3.373
macrocell1 U(1,0) 1 Net_20 Net_20/main_0 Net_20/q 3.350
Route 1 Net_20 Net_20/q Tx_1(0)/pin_input 6.207
iocell3 P12[6] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.220
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000