Static Timing Analysis

Project : Psoc5test
Build Time : 01/02/17 11:29:11
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 52.477 MHz
Clock_1 CyMASTER_CLK 2.000 MHz 2.000 MHz 43.256 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 500ns(2 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:rx_state_1\/q \UART_1:BUART:sRX:RxBitCounter\/load 43.256 MHz 23.118 476.882
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(3,5) 1 \UART_1:BUART:rx_state_1\ \UART_1:BUART:rx_state_1\/clock_0 \UART_1:BUART:rx_state_1\/q 1.250
Route 1 \UART_1:BUART:rx_state_1\ \UART_1:BUART:rx_state_1\/q \UART_1:BUART:rx_counter_load\/main_0 8.738
macrocell1 U(3,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 4.420
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:sRX:RxBitCounter\/load 47.123 MHz 21.221 478.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(3,2) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_counter_load\/main_3 6.403
macrocell5 U(3,4) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_3 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 4.858
count7cell U(2,2) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_1\/q \UART_2:BUART:sRX:RxBitCounter\/load 48.876 MHz 20.460 479.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell30 U(2,2) 1 \UART_2:BUART:rx_state_1\ \UART_2:BUART:rx_state_1\/clock_0 \UART_2:BUART:rx_state_1\/q 1.250
Route 1 \UART_2:BUART:rx_state_1\ \UART_2:BUART:rx_state_1\/q \UART_2:BUART:rx_counter_load\/main_0 5.642
macrocell5 U(3,4) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_0 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 4.858
count7cell U(2,2) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:sRX:RxSts\/status_4 48.984 MHz 20.415 479.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,5) 1 \UART_2:BUART:sRX:RxShifter:u0\ \UART_2:BUART:sRX:RxShifter:u0\/clock \UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_2:BUART:rx_fifofull\ \UART_2:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_2:BUART:rx_status_4\/main_1 5.171
macrocell7 U(3,1) 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/main_1 \UART_2:BUART:rx_status_4\/q 3.350
Route 1 \UART_2:BUART:rx_status_4\ \UART_2:BUART:rx_status_4\/q \UART_2:BUART:sRX:RxSts\/status_4 7.814
statusicell2 U(3,4) 1 \UART_2:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART_2:BUART:rx_state_3\/q \UART_2:BUART:sRX:RxBitCounter\/load 51.345 MHz 19.476 480.524
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(2,4) 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/clock_0 \UART_2:BUART:rx_state_3\/q 1.250
Route 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/q \UART_2:BUART:rx_counter_load\/main_2 4.658
macrocell5 U(3,4) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_2 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 4.858
count7cell U(2,2) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:rx_state_1\/q \UART_3:BUART:sRX:RxBitCounter\/load 51.757 MHz 19.321 480.679
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell43 U(2,2) 1 \UART_3:BUART:rx_state_1\ \UART_3:BUART:rx_state_1\/clock_0 \UART_3:BUART:rx_state_1\/q 1.250
Route 1 \UART_3:BUART:rx_state_1\ \UART_3:BUART:rx_state_1\/q \UART_3:BUART:rx_counter_load\/main_0 5.713
macrocell9 U(2,5) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_0 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 3.648
count7cell U(2,3) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:rx_state_0\/q \UART_3:BUART:sRX:RxBitCounter\/load 52.491 MHz 19.051 480.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(2,4) 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/clock_0 \UART_3:BUART:rx_state_0\/q 1.250
Route 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/q \UART_3:BUART:rx_counter_load\/main_1 5.443
macrocell9 U(2,5) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_1 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 3.648
count7cell U(2,3) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_0\/q \UART_2:BUART:sRX:RxBitCounter\/load 54.253 MHz 18.432 481.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,4) 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/clock_0 \UART_2:BUART:rx_state_0\/q 1.250
Route 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/q \UART_2:BUART:rx_counter_load\/main_1 3.614
macrocell5 U(3,4) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_1 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 4.858
count7cell U(2,2) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 55.288 MHz 18.087 481.913
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(3,3) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 3.707
macrocell1 U(3,2) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 4.420
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:rx_state_0\/q \UART_3:BUART:sRX:RxShifter:u0\/cs_addr_1 56.702 MHz 17.636 482.364
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell44 U(2,4) 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/clock_0 \UART_3:BUART:rx_state_0\/q 1.250
Route 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/q \UART_3:BUART:sRX:RxShifter:u0\/cs_addr_1 10.376
datapathcell3 U(2,1) 1 \UART_3:BUART:sRX:RxShifter:u0\ SETUP 6.010
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_2(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 52.477 MHz 19.056 22.611
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 4.185
datapathcell2 U(3,5) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_3 53.373 MHz 18.736 22.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_0 5.524
macrocell2 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_state_0\/main_3 4.164
macrocell18 U(3,2) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_3 53.373 MHz 18.736 22.931
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_0 5.524
macrocell2 U(3,4) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:rx_status_3\/main_3 4.164
macrocell27 U(3,2) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_3 54.873 MHz 18.224 23.443
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb \UART_3:BUART:rx_postpoll\/main_0 5.592
macrocell10 U(2,3) 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/main_0 \UART_3:BUART:rx_postpoll\/q 3.350
Route 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/q \UART_3:BUART:rx_state_2\/main_3 3.991
macrocell47 U(2,5) 1 \UART_3:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_1\/main_3 54.984 MHz 18.187 23.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:rx_state_1\/main_3 3.276
macrocell30 U(2,2) 1 \UART_2:BUART:rx_state_1\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_break_detect\/main_3 54.984 MHz 18.187 23.480
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:rx_break_detect\/main_3 3.276
macrocell41 U(2,2) 1 \UART_2:BUART:rx_break_detect\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_2\/main_3 55.006 MHz 18.180 23.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:rx_state_2\/main_3 3.269
macrocell34 U(3,2) 1 \UART_2:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:sRX:RxShifter:u0\/route_si 55.021 MHz 18.175 23.492
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb \UART_3:BUART:rx_postpoll\/main_0 5.592
macrocell10 U(2,3) 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/main_0 \UART_3:BUART:rx_postpoll\/q 3.350
Route 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/q \UART_3:BUART:sRX:RxShifter:u0\/route_si 3.982
datapathcell3 U(2,1) 1 \UART_3:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_0\/main_3 55.024 MHz 18.174 23.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:rx_state_0\/main_3 3.263
macrocell31 U(2,4) 1 \UART_2:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_status_3\/main_3 55.024 MHz 18.174 23.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 5.590
macrocell6 U(2,3) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:rx_status_3\/main_3 3.263
macrocell40 U(2,4) 1 \UART_2:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 1.575
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(2,4) 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/clock_0 \UART_2:BUART:rx_status_3\/q 1.250
Route 1 \UART_2:BUART:rx_status_3\ \UART_2:BUART:rx_status_3\/q \UART_2:BUART:sRX:RxSts\/status_3 2.325
statusicell2 U(3,4) 1 \UART_2:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_3:BUART:rx_status_1\/q \UART_3:BUART:sRX:RxSts\/status_1 2.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(2,2) 1 \UART_3:BUART:rx_status_1\ \UART_3:BUART:rx_status_1\/clock_0 \UART_3:BUART:rx_status_1\/q 1.250
Route 1 \UART_3:BUART:rx_status_1\ \UART_3:BUART:rx_status_1\/q \UART_3:BUART:sRX:RxSts\/status_1 2.907
statusicell3 U(2,1) 1 \UART_3:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:rx_status_1\/q \UART_1:BUART:sRX:RxSts\/status_1 2.888
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell26 U(3,5) 1 \UART_1:BUART:rx_status_1\ \UART_1:BUART:rx_status_1\/clock_0 \UART_1:BUART:rx_status_1\/q 1.250
Route 1 \UART_1:BUART:rx_status_1\ \UART_1:BUART:rx_status_1\/q \UART_1:BUART:sRX:RxSts\/status_1 3.638
statusicell1 U(3,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_status_1\/main_6 2.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_status_1\/main_6 2.307
macrocell26 U(3,5) 1 \UART_1:BUART:rx_status_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_break_detect\/main_7 2.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_break_detect\/main_7 2.307
macrocell28 U(3,5) 1 \UART_1:BUART:rx_break_detect\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:rx_status_1\/q \UART_2:BUART:sRX:RxSts\/status_1 2.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(2,2) 1 \UART_2:BUART:rx_status_1\ \UART_2:BUART:rx_status_1\/clock_0 \UART_2:BUART:rx_status_1\/q 1.250
Route 1 \UART_2:BUART:rx_status_1\ \UART_2:BUART:rx_status_1\/q \UART_2:BUART:sRX:RxSts\/status_1 3.677
statusicell2 U(3,4) 1 \UART_2:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_0 \UART_3:BUART:rx_bitclk_enable\/main_2 2.928
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,3) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_3:BUART:rx_count_0\ \UART_3:BUART:sRX:RxBitCounter\/count_0 \UART_3:BUART:rx_bitclk_enable\/main_2 2.308
macrocell48 U(2,3) 1 \UART_3:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_status_1\/main_8 2.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN4_4 \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_status_1\/main_8 2.314
macrocell26 U(3,5) 1 \UART_1:BUART:rx_status_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_break_detect\/main_9 2.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,5) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN4_4 \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_break_detect\/main_9 2.314
macrocell28 U(3,5) 1 \UART_1:BUART:rx_break_detect\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_3 \UART_2:BUART:rx_status_1\/main_9 2.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,2) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_3 0.620
Route 1 MODIN9_3 \UART_2:BUART:sRX:RxBitCounter\/count_3 \UART_2:BUART:rx_status_1\/main_9 2.319
macrocell39 U(2,2) 1 \UART_2:BUART:rx_status_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 6.464
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 4.683
macrocell55 U(2,4) 1 \UART_3:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 7.142
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 4.681
macrocell42 U(3,4) 1 \UART_2:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb MODIN11_1/main_2 7.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb MODIN11_1/main_2 5.592
macrocell50 U(2,3) 1 MODIN11_1 HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb MODIN11_0/main_2 7.373
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb MODIN11_0/main_2 5.592
macrocell51 U(2,3) 1 MODIN11_0 HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_6 7.386
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[5] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 1.781
Route 1 Net_33 Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_6 5.605
macrocell47 U(2,5) 1 \UART_3:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb MODIN1_1/main_2 7.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_7 Rx_1(0)/fb MODIN1_1/main_2 5.524
macrocell24 U(3,4) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb MODIN1_0/main_2 7.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_7 Rx_1(0)/fb MODIN1_0/main_2 5.524
macrocell25 U(3,4) 1 MODIN1_0 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_6 7.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P0[7] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.188
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_6 5.744
macrocell21 U(3,3) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb MODIN6_1/main_2 8.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb MODIN6_1/main_2 5.590
macrocell37 U(2,5) 1 MODIN6_1 HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb MODIN6_0/main_2 8.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P0[6] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.461
Route 1 Net_20 Rx_2(0)/fb MODIN6_0/main_2 5.590
macrocell38 U(2,5) 1 MODIN6_0 HOLD 0.000
Clock Skew 0.000
+ Input To Output Section
Source Destination Delay (ns)
BREAKPIN(0)_PAD:in TX(0)_PAD 41.009
Type Location Fanout Instance/Net Source Dest Delay (ns)
Psoc5test 1 BREAKPIN(0)_PAD:in BREAKPIN(0)_PAD:in BREAKPIN(0)_PAD:in 0.000
Route 1 BREAKPIN(0)_PAD BREAKPIN(0)_PAD:in BREAKPIN(0)/pad_in 0.000
iocell6 P0[0] 1 BREAKPIN(0) BREAKPIN(0)/pad_in BREAKPIN(0)/fb 7.922
Route 1 Net_81 BREAKPIN(0)/fb Net_85/main_1 6.637
macrocell16 U(3,1) 1 Net_85 Net_85/main_1 Net_85/q 3.350
Route 1 Net_85 Net_85/q TX(0)/pin_input 7.298
iocell5 P0[1] 1 TX(0) TX(0)/pin_input TX(0)/pad_out 15.802
Route 1 TX(0)_PAD TX(0)/pad_out TX(0)_PAD 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
\UARTOUT:BUART:txn\/q TX(0)_PAD 30.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(2,1) 1 \UARTOUT:BUART:txn\ \UARTOUT:BUART:txn\/clock_0 \UARTOUT:BUART:txn\/q 1.250
Route 1 \UARTOUT:BUART:txn\ \UARTOUT:BUART:txn\/q Net_85/main_0 2.608
macrocell16 U(3,1) 1 Net_85 Net_85/main_0 Net_85/q 3.350
Route 1 Net_85 Net_85/q TX(0)/pin_input 7.298
iocell5 P0[1] 1 TX(0) TX(0)/pin_input TX(0)/pad_out 15.802
Route 1 TX(0)_PAD TX(0)/pad_out TX(0)_PAD 0.000
Clock Clock path delay 0.000