Static Timing Analysis

Project : Test SAR to VDAC DMA
Build Time : 07/24/15 15:08:45
Device : CY8C5888LTQ-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_1_theACLK(routed) ADC_SAR_1_theACLK(routed) 1.043 MHz 1.043 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_1_theACLK CyMASTER_CLK 1.043 MHz 1.043 MHz N/A
WaveDAC8_1_DacClk CyMASTER_CLK 100.000 kHz 100.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
WaveDAC8_1_DacClk(routed) WaveDAC8_1_DacClk(routed) 100.000 kHz 100.000 kHz N/A