Static Timing Analysis

Project : SPI_Design02_Slave
Build Time : 04/02/19 17:24:31
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock CyMASTER_CLK 500.000 kHz 500.000 kHz 75.850 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
s_sclk_pin(0)_PAD s_sclk_pin(0)_PAD UNKNOWN UNKNOWN 46.049 MHz
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 2000ns(500 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 75.850 MHz 13.184 1986.816
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 1.020
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 4.126
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 83.472 MHz 11.980 1988.020
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.922
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 86.371 MHz 11.578 1988.422
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.290
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 86.475 MHz 11.564 1988.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,4) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.292
macrocell4 U(3,4) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.172
statusicell2 U(2,4) 1 \SPIS:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 88.044 MHz 11.358 1988.642
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.020
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.316
macrocell4 U(3,4) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.172
statusicell2 U(2,4) 1 \SPIS:BSPIS:RxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 98.834 MHz 10.118 1989.882
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.922
macrocell3 U(3,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.326
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 102.923 MHz 9.716 1990.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.290
macrocell3 U(3,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.326
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 134.192 MHz 7.452 1992.548
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 1.020
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.922
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ SETUP 3.510
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 146.071 MHz 6.846 1993.154
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 1.020
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.316
macrocell11 U(3,4) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 92.098 MHz 10.858
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,3) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.292
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -0.928
Path Delay Requirement : 5000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 94.724 MHz 10.557
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.340
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 94.787 MHz 10.550
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.333
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 94.823 MHz 10.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.329
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 94.940 MHz 10.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.316
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP -0.000
Clock Skew -0.928
Path Delay Requirement : 10000ns
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 66.503 MHz 15.037
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.340
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 66.534 MHz 15.030
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.333
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 66.551 MHz 15.026
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.329
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 66.609 MHz 15.013
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.316
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 4.480
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 86.237 MHz 11.596
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 1.940
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 2.340
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 86.289 MHz 11.589
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 1.940
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 2.333
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 86.319 MHz 11.585
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 1.940
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 2.329
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 86.415 MHz 11.572
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 1.940
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 2.316
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Skew -0.928
+ Hold Subsection
Source Destination Slack (ns) Violation
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.350
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:mosi_buf_overrun_fin\/main_0 2.316
macrocell11 U(3,4) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 3.272
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:dpcounter_one_reg\/main_0 2.922
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ HOLD 0.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_6 6.948
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:byte_complete\/main_0 2.922
macrocell3 U(3,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_0 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.326
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_6 7.216
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:byte_complete\/main_1 2.290
macrocell3 U(3,3) 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/main_1 \SPIS:BSPIS:byte_complete\/q 3.350
Route 1 \SPIS:BSPIS:byte_complete\ \SPIS:BSPIS:byte_complete\/q \SPIS:BSPIS:TxStsReg\/status_6 2.326
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:RxStsReg\/status_5 8.188
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_3\ \SPIS:BSPIS:sync_3\/clock \SPIS:BSPIS:sync_3\/out 0.350
Route 1 \SPIS:BSPIS:mosi_buf_overrun_reg\ \SPIS:BSPIS:sync_3\/out \SPIS:BSPIS:rx_buf_overrun\/main_0 2.316
macrocell4 U(3,4) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_0 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.172
statusicell2 U(2,4) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:TxStsReg\/status_0 8.810
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_1\ \SPIS:BSPIS:sync_1\/clock \SPIS:BSPIS:sync_1\/out 0.350
Route 1 \SPIS:BSPIS:dpcounter_one_fin\ \SPIS:BSPIS:sync_1\/out \SPIS:BSPIS:tx_status_0\/main_0 2.922
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_0 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:RxStsReg\/status_5 9.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,4) 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/clock_0 \SPIS:BSPIS:mosi_buf_overrun_fin\/q 1.250
Route 1 \SPIS:BSPIS:mosi_buf_overrun_fin\ \SPIS:BSPIS:mosi_buf_overrun_fin\/q \SPIS:BSPIS:rx_buf_overrun\/main_1 2.292
macrocell4 U(3,4) 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/main_1 \SPIS:BSPIS:rx_buf_overrun\/q 3.350
Route 1 \SPIS:BSPIS:rx_buf_overrun\ \SPIS:BSPIS:rx_buf_overrun\/q \SPIS:BSPIS:RxStsReg\/status_5 4.172
statusicell2 U(2,4) 1 \SPIS:BSPIS:RxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:TxStsReg\/status_0 9.078
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(3,3) 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/clock_0 \SPIS:BSPIS:dpcounter_one_reg\/q 1.250
Route 1 \SPIS:BSPIS:dpcounter_one_reg\ \SPIS:BSPIS:dpcounter_one_reg\/q \SPIS:BSPIS:tx_status_0\/main_1 2.290
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_1 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
\SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:TxStsReg\/status_0 10.014
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,4) 1 \SPIS:BSPIS:sync_2\ \SPIS:BSPIS:sync_2\/clock \SPIS:BSPIS:sync_2\/out 0.350
Route 1 \SPIS:BSPIS:miso_tx_empty_reg_fin\ \SPIS:BSPIS:sync_2\/out \SPIS:BSPIS:tx_status_0\/main_2 4.126
macrocell7 U(3,3) 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/main_2 \SPIS:BSPIS:tx_status_0\/q 3.350
Route 1 \SPIS:BSPIS:tx_status_0\ \SPIS:BSPIS:tx_status_0\/q \SPIS:BSPIS:TxStsReg\/status_0 4.188
statusicell1 U(2,3) 1 \SPIS:BSPIS:TxStsReg\ HOLD -2.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 5007.318
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,3) 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/clock_0 \SPIS:BSPIS:mosi_tmp\/q 1.250
Route 1 \SPIS:BSPIS:mosi_tmp\ \SPIS:BSPIS:mosi_tmp\/q \SPIS:BSPIS:mosi_to_dp\/main_4 2.292
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_4 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -0.928
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5005.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.316
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5005.836
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.329
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5005.840
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.333
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/f1_load 5005.847
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.340
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/f1_load 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -3.390
Clock Skew -0.928
Source Destination Slack (ns) Violation
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:mosi_to_dp\/main_3 2.316
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_3 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.725
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:mosi_to_dp\/main_2 2.329
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_2 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.729
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:mosi_to_dp\/main_1 2.333
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_1 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/route_si 6.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:mosi_to_dp\/main_0 2.340
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_0 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD -1.570
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.213
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_0 0.620
Route 1 \SPIS:BSPIS:count_0\ \SPIS:BSPIS:BitCounter\/count_0 \SPIS:BSPIS:tx_load\/main_3 2.316
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_3 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.226
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_1 0.620
Route 1 \SPIS:BSPIS:count_1\ \SPIS:BSPIS:BitCounter\/count_1 \SPIS:BSPIS:tx_load\/main_2 2.329
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_2 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.230
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_2 0.620
Route 1 \SPIS:BSPIS:count_2\ \SPIS:BSPIS:BitCounter\/count_2 \SPIS:BSPIS:tx_load\/main_1 2.333
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_1 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -0.928
\SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 9.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ \SPIS:BSPIS:BitCounter\/clock_n \SPIS:BSPIS:BitCounter\/count_3 0.620
Route 1 \SPIS:BSPIS:count_3\ \SPIS:BSPIS:BitCounter\/count_3 \SPIS:BSPIS:tx_load\/main_0 2.340
macrocell2 U(3,3) 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/main_0 \SPIS:BSPIS:tx_load\/q 3.350
Route 1 \SPIS:BSPIS:tx_load\ \SPIS:BSPIS:tx_load\/q \SPIS:BSPIS:sR8:Dp:u0\/cs_addr_0 3.855
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ HOLD 0.000
Clock Skew -0.928
+ Input To Output Section
Source Destination Delay (ns)
s_ss_pin(0)_PAD s_miso_pin(0)_PAD 37.568
Type Location Fanout Instance/Net Source Dest Delay (ns)
SPI_Design02_Slave 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)_PAD 0.000
Route 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)/pad_in 0.000
iocell3 P0[6] 1 s_ss_pin(0) s_ss_pin(0)/pad_in s_ss_pin(0)/fb 7.354
Route 1 Net_109 s_ss_pin(0)/fb Net_37/main_0 5.910
macrocell5 U(3,4) 1 Net_37 Net_37/main_0 Net_37/q 3.350
Route 1 Net_37 Net_37/q s_miso_pin(0)/pin_input 5.495
iocell4 P0[2] 1 s_miso_pin(0) s_miso_pin(0)/pin_input s_miso_pin(0)/pad_out 15.459
Route 1 s_miso_pin(0)_PAD s_miso_pin(0)/pad_out s_miso_pin(0)_PAD 0.000
+ Input To Clock Section
+ s_sclk_pin(0)_PAD
Source Destination Delay (ns)
s_ss_pin(0)_PAD \SPIS:BSPIS:BitCounter\/enable 10.271
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_ss_pin(0)_PAD s_ss_pin(0)_PAD s_ss_pin(0)/pad_in 0.000
iocell3 P0[6] 1 s_ss_pin(0) s_ss_pin(0)/pad_in s_ss_pin(0)/fb 7.354
Route 1 Net_109 s_ss_pin(0)/fb \SPIS:BSPIS:inv_ss\/main_0 5.902
macrocell1 U(2,4) 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/main_0 \SPIS:BSPIS:inv_ss\/q 3.350
Route 1 \SPIS:BSPIS:inv_ss\ \SPIS:BSPIS:inv_ss\/q \SPIS:BSPIS:BitCounter\/enable 3.193
count7cell U(3,3) 1 \SPIS:BSPIS:BitCounter\ SETUP 4.060
Clock Clock path delay -13.588
s_mosi_pin(0)_PAD \SPIS:BSPIS:sR8:Dp:u0\/route_si 7.979
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_mosi_pin(0)_PAD s_mosi_pin(0)_PAD s_mosi_pin(0)/pad_in 0.000
iocell1 P0[0] 1 s_mosi_pin(0) s_mosi_pin(0)/pad_in s_mosi_pin(0)/fb 7.922
Route 1 Net_33 s_mosi_pin(0)/fb \SPIS:BSPIS:mosi_to_dp\/main_5 6.329
macrocell9 U(3,3) 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/main_5 \SPIS:BSPIS:mosi_to_dp\/q 3.350
Route 1 \SPIS:BSPIS:mosi_to_dp\ \SPIS:BSPIS:mosi_to_dp\/q \SPIS:BSPIS:sR8:Dp:u0\/route_si 2.924
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ SETUP 1.970
Clock Clock path delay -14.516
s_mosi_pin(0)_PAD \SPIS:BSPIS:mosi_tmp\/main_0 4.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 s_mosi_pin(0)_PAD s_mosi_pin(0)_PAD s_mosi_pin(0)/pad_in 0.000
iocell1 P0[0] 1 s_mosi_pin(0) s_mosi_pin(0)/pad_in s_mosi_pin(0)/fb 7.922
Route 1 Net_33 s_mosi_pin(0)/fb \SPIS:BSPIS:mosi_tmp\/main_0 6.329
macrocell12 U(3,3) 1 \SPIS:BSPIS:mosi_tmp\ SETUP 3.510
Clock Clock path delay -13.588
+ Clock To Output Section
+ s_sclk_pin(0)_PAD
Source Destination Delay (ns)
\SPIS:BSPIS:sR8:Dp:u0\/so_comb s_miso_pin(0)_PAD 50.288
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,4) 1 \SPIS:BSPIS:sR8:Dp:u0\ \SPIS:BSPIS:sR8:Dp:u0\/clock \SPIS:BSPIS:sR8:Dp:u0\/so_comb 9.160
Route 1 \SPIS:BSPIS:miso_from_dp\ \SPIS:BSPIS:sR8:Dp:u0\/so_comb Net_37/main_1 2.308
macrocell5 U(3,4) 1 Net_37 Net_37/main_1 Net_37/q 3.350
Route 1 Net_37 Net_37/q s_miso_pin(0)/pin_input 5.495
iocell4 P0[2] 1 s_miso_pin(0) s_miso_pin(0)/pin_input s_miso_pin(0)/pad_out 15.459
Route 1 s_miso_pin(0)_PAD s_miso_pin(0)/pad_out s_miso_pin(0)_PAD 0.000
Clock Clock path delay 14.516