Static Timing Analysis

Project : Circulus
Build Time : 07/27/15 13:34:13
Device : CY8C5868AXI-LP035
Temperature : 0C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ext_clk CyMASTER_CLK 1.000 kHz 1.000 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
ext_clk(routed) ext_clk(routed) 1.000 kHz 1.000 kHz N/A
+ Clock To Output Section
+ ext_clk(routed)
Source Destination Delay (ns)
ClockBlock/dclk_0 clk(0)_PAD 23.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_183_local ClockBlock/dclk_0 clk(0)/pin_input 7.890
iocell16 P1[5] 1 clk(0) clk(0)/pin_input clk(0)/pad_out 15.342
Route 1 clk(0)_PAD clk(0)/pad_out clk(0)_PAD 0.000
Clock Clock path delay 0.000
ClockBlock/dclk_0 clk(0)_PAD 23.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
clockblockcell F(Clock,0) 1 ClockBlock Input Delay ClockBlock/dclk_0 0.000
Route 1 Net_183_local ClockBlock/dclk_0 clk(0)/pin_input 7.890
iocell16 P1[5] 1 clk(0) clk(0)/pin_input clk(0)/pad_out 15.342
Route 1 clk(0)_PAD clk(0)/pad_out clk(0)_PAD 0.000
Clock Clock path delay 0.000