Static Timing Analysis

Project : psoc learning
Build Time : 09/11/19 15:45:19
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus_glb_ff ClockBlock/clk_bus_glb_ff UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 60.423 MHz
UART_IntClock CyMASTER_CLK 76.677 kHz 76.677 kHz 55.903 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 60.423 MHz 16.550 25.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 5.470
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.251
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 79.346 MHz 12.603 29.064
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 7.084
macrocell21 U(1,2) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 83.970 MHz 11.909 29.758
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 6.390
macrocell23 U(0,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 84.104 MHz 11.890 29.777
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 6.371
macrocell22 U(0,1) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 90.860 MHz 11.006 30.661
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 5.487
macrocell18 U(1,0) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 91.000 MHz 10.989 30.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 5.470
macrocell15 U(1,0) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 91.000 MHz 10.989 30.678
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.470
macrocell24 U(1,0) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 55.903 MHz 17.888 13023.779
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,0) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 5.613
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.600 MHz 17.668 13023.999
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(0,2) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 4.578
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 57.981 MHz 17.247 13024.420
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 5.217
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 59.393 MHz 16.837 13024.830
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,0) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 4.562
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.196 MHz 16.341 13025.326
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(1,2) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 3.251
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 61.421 MHz 16.281 13025.386
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 4.006
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 61.667 MHz 16.216 13025.451
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(1,2) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 5.895
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.251
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.774 MHz 16.188 13025.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(0,2) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 3.098
macrocell2 U(0,2) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.300
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 63.016 MHz 15.869 13025.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,1) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.594
macrocell5 U(1,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 68.861 MHz 14.522 13027.145
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(1,2) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 4.763
macrocell3 U(1,2) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.329
statusicell1 U(1,2) 1 \UART:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 7.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_state_0\/main_0 5.470
macrocell15 U(1,0) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_last\/main_0 7.479
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_last\/main_0 5.470
macrocell24 U(1,0) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 7.496
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_state_2\/main_0 5.487
macrocell18 U(1,0) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 8.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:pollcount_0\/main_0 6.371
macrocell22 U(0,1) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 8.399
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_status_3\/main_0 6.390
macrocell23 U(0,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 9.093
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:pollcount_1\/main_0 7.084
macrocell21 U(1,2) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 13.080
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P12[6] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.009
Route 1 Net_80 Rx_1(0)/fb \UART:BUART:rx_postpoll\/main_0 5.470
macrocell6 U(1,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.251
datapathcell3 U(0,0) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.117
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(0,1) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.867
statusicell2 U(0,0) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.787
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.597
macrocell12 U(0,2) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.605
macrocell9 U(0,2) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.795
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,2) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.605
macrocell10 U(0,2) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 2.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_load_fifo\/main_7 2.307
macrocell16 U(1,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 2.927
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART:BUART:rx_count_4\ \UART:BUART:sRX:RxBitCounter\/count_4 \UART:BUART:rx_state_3\/main_7 2.307
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.312
macrocell16 U(1,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_3\/main_5 2.932
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_3\/main_5 2.312
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.933
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.313
macrocell16 U(1,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 2.933
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_3\/main_6 2.313
macrocell17 U(1,1) 1 \UART:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ ClockBlock/clk_bus_glb_ff
Source Destination Delay (ns)
\I2C:I2C_FF\/sda_out SDA_1(0)_PAD:out 24.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/sda_out 1.000
Route 1 \I2C:sda_x_wire\ \I2C:I2C_FF\/sda_out SDA_1(0)/pin_input 7.910
iocell2 P12[1] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 15.933
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:I2C_FF\/scl_out SCL_1(0)_PAD:out 24.785
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/scl_out 1.000
Route 1 \I2C:Net_643_0\ \I2C:I2C_FF\/scl_out SCL_1(0)/pin_input 7.930
iocell1 P12[0] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 15.855
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx_1(0)_PAD 30.730
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,2) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_75/main_0 3.404
macrocell1 U(0,1) 1 Net_75 Net_75/main_0 Net_75/q 3.350
Route 1 Net_75 Net_75/q Tx_1(0)/pin_input 5.759
iocell4 P12[7] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 16.967
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000