Static Timing Analysis

Project : isgMain_v2.1
Build Time : 06/11/18 18:36:20
Device : CY8C5468AXI-LP042
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk ADC_Ext_CP_Clk 24.000 MHz 24.000 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 24.000 MHz 24.000 MHz N/A
ClockBlock/aclk_glb_ff_1 ClockBlock/aclk_glb_ff_1 UNKNOWN UNKNOWN N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ClockX CyMASTER_CLK 24.000 MHz 24.000 MHz 38.781 MHz
ADC_theACLK CyMASTER_CLK 2.182 MHz 2.182 MHz N/A
UART_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 55.451 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyScBoostClk CyScBoostClk 12.000 MHz 12.000 MHz N/A
\ADC:DSM\/dec_clock \ADC:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\Timer5s:TimerUDB:sT32:timerdp:u0\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 38.781 MHz 25.786 15.881
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/clock \Timer5s:TimerUDB:sT32:timerdp:u0\/z0 0.760
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/z0 \Timer5s:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/z0i \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 1.210
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer5s:TimerUDB:per_zero\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.906
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/ci \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/ci \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u0\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 39.110 MHz 25.569 16.098
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u0\ \Timer1s:TimerUDB:sT32:timerdp:u0\/clock \Timer1s:TimerUDB:sT32:timerdp:u0\/z0 0.760
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u0\/z0 \Timer1s:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/z0i \Timer1s:TimerUDB:sT32:timerdp:u1\/z0 1.210
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/z0 \Timer1s:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/z0i \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer1s:TimerUDB:per_zero\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.689
datapathcell8 U(2,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u0\ \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/ci \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/ci \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\TimerXs:TimerUDB:sT32:timerdp:u0\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 39.200 MHz 25.510 16.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ \TimerXs:TimerUDB:sT32:timerdp:u0\/clock \TimerXs:TimerUDB:sT32:timerdp:u0\/z0 0.760
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u0.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u0\/z0 \TimerXs:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/z0i \TimerXs:TimerUDB:sT32:timerdp:u1\/z0 1.210
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/z0 \TimerXs:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/z0i \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \TimerXs:TimerUDB:per_zero\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.630
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/ci \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/ci \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u1\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 40.690 MHz 24.576 17.091
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/clock \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 0.760
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer5s:TimerUDB:per_zero\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.906
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/ci \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/ci \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u1\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 41.053 MHz 24.359 17.308
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/clock \Timer1s:TimerUDB:sT32:timerdp:u1\/z0 0.760
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/z0 \Timer1s:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/z0i \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer1s:TimerUDB:per_zero\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.689
datapathcell8 U(2,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u0\ \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/ci \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/ci \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\TimerXs:TimerUDB:sT32:timerdp:u1\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 41.152 MHz 24.300 17.367
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/clock \TimerXs:TimerUDB:sT32:timerdp:u1\/z0 0.760
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/z0 \TimerXs:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/z0i \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \TimerXs:TimerUDB:per_zero\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.630
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/ci \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/ci \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u2\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 42.797 MHz 23.366 18.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/clock \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 0.760
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer5s:TimerUDB:per_zero\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.906
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/ci \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/ci \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u2\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 43.198 MHz 23.149 18.518
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/clock \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 0.760
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/z0 \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0i \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer1s:TimerUDB:per_zero\ \Timer1s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.689
datapathcell8 U(2,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u0\ \Timer1s:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/ci \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/ci \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\TimerXs:TimerUDB:sT32:timerdp:u2\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 43.309 MHz 23.090 18.577
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/clock \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 0.760
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.z0__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/z0 \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0i \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \TimerXs:TimerUDB:per_zero\ \TimerXs:TimerUDB:sT32:timerdp:u3\/z0_comb \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 3.630
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_0 \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb 5.130
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/ci \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/ci \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u0\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 44.470 MHz 22.487 19.180
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/clock \Timer5s:TimerUDB:sT32:timerdp:u0\/z0 0.760
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/z0 \Timer5s:TimerUDB:sT32:timerdp:u1\/z0i 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/z0i \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 1.210
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/z0 \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0i \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 1.210
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.z0__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/z0 \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0i \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb 2.740
Route 1 \Timer5s:TimerUDB:per_zero\ \Timer5s:TimerUDB:sT32:timerdp:u3\/z0_comb \Timer5s:TimerUDB:sT32:timerdp:u1\/cs_addr_0 3.907
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/cs_addr_0 \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb 5.130
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/ci \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb 3.300
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ SETUP 4.230
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.451 MHz 18.034 1065.299
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(2,4) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.926
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.318
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.821 MHz 17.599 1065.734
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(2,3) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 4.491
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.318
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.004 MHz 16.948 1066.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(2,3) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.840
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.318
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART:BUART:rx_state_0\/q \UART:BUART:sRX:RxBitCounter\/load 59.909 MHz 16.692 1066.641
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell19 U(2,5) 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/clock_0 \UART:BUART:rx_state_0\/q 1.250
Route 1 \UART:BUART:rx_state_0\ \UART:BUART:rx_state_0\/q \UART:BUART:rx_counter_load\/main_1 4.418
macrocell5 U(2,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_1 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.314
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 63.625 MHz 15.717 1067.616
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell25 U(2,4) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_1 5.343
macrocell6 U(2,5) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.304
datapathcell3 U(3,5) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 64.338 MHz 15.543 1067.790
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(3,5) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 3.269
macrocell5 U(2,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.314
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:sRX:RxBitCounter\/load 65.053 MHz 15.372 1067.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(3,5) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_counter_load\/main_3 3.098
macrocell5 U(2,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_3 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.314
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 65.569 MHz 15.251 1068.082
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(3,5) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.290
macrocell7 U(3,5) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 5.531
statusicell2 U(3,5) 1 \UART:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 65.742 MHz 15.211 1068.122
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(2,5) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 2.937
macrocell5 U(2,5) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.314
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 66.089 MHz 15.131 1068.202
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 3.083
macrocell2 U(2,4) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.318
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ \TimerXs:TimerUDB:sT32:timerdp:u0\/clock \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb 2.140
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u0\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u2\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(3,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u1\ \TimerXs:TimerUDB:sT32:timerdp:u1\/clock \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb 2.140
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u1\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(3,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u2\ \TimerXs:TimerUDB:sT32:timerdp:u2\/clock \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb 2.140
Route 1 \TimerXs:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \TimerXs:TimerUDB:sT32:timerdp:u2\/co_msb \TimerXs:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell7 U(2,1) 1 \TimerXs:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(2,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u0\ \Timer1s:TimerUDB:sT32:timerdp:u0\/clock \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb 2.140
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u2\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell9 U(3,3) 1 \Timer1s:TimerUDB:sT32:timerdp:u1\ \Timer1s:TimerUDB:sT32:timerdp:u1\/clock \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb 2.140
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(3,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u2\ \Timer1s:TimerUDB:sT32:timerdp:u2\/clock \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb 2.140
Route 1 \Timer1s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer1s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer1s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell11 U(2,2) 1 \Timer1s:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u1\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell12 U(1,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u0\ \Timer5s:TimerUDB:sT32:timerdp:u0\/clock \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb 2.140
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u0.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u0\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u1\/ci 0.000
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ HOLD 0.000
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(0,1) 1 \Timer5s:TimerUDB:sT32:timerdp:u1\ \Timer5s:TimerUDB:sT32:timerdp:u1\/clock \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb 2.140
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u1.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u1\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u2\/ci 0.000
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ HOLD 0.000
Clock Skew 0.000
\Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 2.140
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell14 U(0,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u2\ \Timer5s:TimerUDB:sT32:timerdp:u2\/clock \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb 2.140
Route 1 \Timer5s:TimerUDB:sT32:timerdp:u2.co_msb__sig\ \Timer5s:TimerUDB:sT32:timerdp:u2\/co_msb \Timer5s:TimerUDB:sT32:timerdp:u3\/ci 0.000
datapathcell15 U(1,0) 1 \Timer5s:TimerUDB:sT32:timerdp:u3\ HOLD 0.000
Clock Skew 0.000
\TimerXs:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_1 2.907
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(2,0) 1 \TimerXs:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\ \TimerXs:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/clock \TimerXs:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 0.360
Route 1 \TimerXs:TimerUDB:control_7\ \TimerXs:TimerUDB:sCTRLReg:SyncCtl:ctrlreg\/control_7 \TimerXs:TimerUDB:sT32:timerdp:u0\/cs_addr_1 2.547
datapathcell4 U(2,0) 1 \TimerXs:TimerUDB:sT32:timerdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 1.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell27 U(2,5) 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/clock_0 \UART:BUART:rx_status_3\/q 1.250
Route 1 \UART:BUART:rx_status_3\ \UART:BUART:rx_status_3\/q \UART:BUART:sRX:RxSts\/status_3 2.324
statusicell2 U(3,5) 1 \UART:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART:BUART:rx_count_0\ \UART:BUART:sRX:RxBitCounter\/count_0 \UART:BUART:rx_bitclk_enable\/main_2 2.299
macrocell23 U(2,5) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.929
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART:BUART:rx_count_2\ \UART:BUART:sRX:RxBitCounter\/count_2 \UART:BUART:rx_bitclk_enable\/main_0 2.309
macrocell23 U(2,5) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.930
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART:BUART:rx_count_1\ \UART:BUART:sRX:RxBitCounter\/count_1 \UART:BUART:rx_bitclk_enable\/main_1 2.310
macrocell23 U(2,5) 1 \UART:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 3.128
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(3,4) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:TxShifter:u0\/cs_addr_0 2.938
datapathcell1 U(2,4) 1 \UART:BUART:sTX:TxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 3.274
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_load_fifo\/main_6 2.654
macrocell20 U(3,5) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 3.274
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_2\/main_7 2.654
macrocell22 U(3,5) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 3.277
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_load_fifo\/main_5 2.657
macrocell20 U(3,5) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 3.277
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART:BUART:rx_count_6\ \UART:BUART:sRX:RxBitCounter\/count_6 \UART:BUART:rx_state_2\/main_6 2.657
macrocell22 U(3,5) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 3.278
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,5) 1 \UART:BUART:sRX:RxBitCounter\ \UART:BUART:sRX:RxBitCounter\/clock \UART:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART:BUART:rx_count_5\ \UART:BUART:sRX:RxBitCounter\/count_5 \UART:BUART:rx_state_0\/main_7 2.658
macrocell19 U(2,5) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ UART_IntClock
Source Destination Delay (ns)
S2(0)_PAD \UART:BUART:sRX:RxShifter:u0\/route_si 25.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 S2(0)_PAD S2(0)_PAD S2(0)/pad_in 0.000
iocell2 P12[3] 1 S2(0) S2(0)/pad_in S2(0)/fb 8.430
Route 1 Net_164 S2(0)/fb \UART:BUART:rx_postpoll\/main_0 8.437
macrocell6 U(2,5) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.304
datapathcell3 U(3,5) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Clock path delay 0.000
+ Clock To Output Section
+ UART_IntClock
Source Destination Delay (ns)
\UART:BUART:txn\/q S1(0)_PAD 29.173
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(2,3) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_162/main_0 2.589
macrocell1 U(3,3) 1 Net_162 Net_162/main_0 Net_162/q 3.350
Route 1 Net_162 Net_162/q S1(0)/pin_input 6.318
iocell13 P12[2] 1 S1(0) S1(0)/pin_input S1(0)/pad_out 15.666
Route 1 S1(0)_PAD S1(0)/pad_out S1(0)_PAD 0.000
Clock Clock path delay 0.000