Static Timing Analysis

Project : I2C_SPI_UART
Build Time : 04/27/16 22:46:12
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz 45.325 MHz
I2C_SCBCLK CyHFCLK 800.000 kHz 800.000 kHz N/A
Clock CyHFCLK 76.677 kHz 76.677 kHz 44.334 MHz
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CyRouted1 CyRouted1 24.000 MHz 24.000 MHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
I2C_SCBCLK(FFB) I2C_SCBCLK(FFB) 800.000 kHz 800.000 kHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 13041.7ns(76.6773 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART:BUART:tx_state_0\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.334 MHz 22.556 13019.111
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,0) 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/clock_0 \UART:BUART:tx_state_0\/q 1.250
Route 1 \UART:BUART:tx_state_0\ \UART:BUART:tx_state_0\/q \UART:BUART:counter_load_not\/main_1 4.207
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_1 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 44.865 MHz 22.289 13019.378
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 1.000
Route 1 \UART:BUART:tx_bitclk_enable_pre\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART:BUART:counter_load_not\/main_2 4.190
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_2 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_1\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.561 MHz 21.477 13020.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,0) 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/clock_0 \UART:BUART:tx_state_1\/q 1.250
Route 1 \UART:BUART:tx_state_1\ \UART:BUART:tx_state_1\/q \UART:BUART:counter_load_not\/main_0 3.128
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_0 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:tx_state_2\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.913 MHz 21.316 13020.351
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,0) 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/clock_0 \UART:BUART:tx_state_2\/q 1.250
Route 1 \UART:BUART:tx_state_2\ \UART:BUART:tx_state_2\/q \UART:BUART:counter_load_not\/main_3 2.967
macrocell2 U(1,0) 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/main_3 \UART:BUART:counter_load_not\/q 3.350
Route 1 \UART:BUART:counter_load_not\ \UART:BUART:counter_load_not\/q \UART:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.229
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 11.520
Clock Skew 0.000
\UART:BUART:pollcount_1\/q \UART:BUART:sRX:RxShifter:u0\/route_si 58.391 MHz 17.126 13024.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/clock_0 \UART:BUART:pollcount_1\/q 1.250
Route 1 \UART:BUART:pollcount_1\ \UART:BUART:pollcount_1\/q \UART:BUART:rx_postpoll\/main_0 4.469
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_0 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:sTX:TxSts\/status_0 62.089 MHz 16.106 13025.561
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,0) 1 \UART:BUART:sTX:TxShifter:u0\ \UART:BUART:sTX:TxShifter:u0\/clock \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:tx_fifo_empty\ \UART:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART:BUART:tx_status_0\/main_3 3.655
macrocell3 U(0,0) 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/main_3 \UART:BUART:tx_status_0\/q 3.350
Route 1 \UART:BUART:tx_status_0\ \UART:BUART:tx_status_0\/q \UART:BUART:sTX:TxSts\/status_0 2.251
statusicell1 U(0,0) 1 \UART:BUART:sTX:TxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:sRX:RxBitCounter\/load 65.535 MHz 15.259 13026.408
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(0,1) 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/clock_0 \UART:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART:BUART:tx_ctrl_mark_last\ \UART:BUART:tx_ctrl_mark_last\/q \UART:BUART:rx_counter_load\/main_0 4.127
macrocell5 U(0,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_0 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:sRX:RxShifter:u0\/route_si 65.802 MHz 15.197 13026.470
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:rx_postpoll\/main_2 2.540
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_2 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
\UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:sRX:RxSts\/status_4 67.467 MHz 14.822 13026.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ \UART:BUART:sRX:RxShifter:u0\/clock \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 5.280
Route 1 \UART:BUART:rx_fifofull\ \UART:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART:BUART:rx_status_4\/main_1 2.312
macrocell7 U(1,1) 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/main_1 \UART:BUART:rx_status_4\/q 3.350
Route 1 \UART:BUART:rx_status_4\ \UART:BUART:rx_status_4\/q \UART:BUART:sRX:RxSts\/status_4 2.310
statusicell2 U(1,1) 1 \UART:BUART:sRX:RxSts\ SETUP 1.570
Clock Skew 0.000
\UART:BUART:rx_state_3\/q \UART:BUART:sRX:RxBitCounter\/load 67.645 MHz 14.783 13026.884
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(0,1) 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/clock_0 \UART:BUART:rx_state_3\/q 1.250
Route 1 \UART:BUART:rx_state_3\ \UART:BUART:rx_state_3\/q \UART:BUART:rx_counter_load\/main_2 3.651
macrocell5 U(0,1) 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/main_2 \UART:BUART:rx_counter_load\/q 3.350
Route 1 \UART:BUART:rx_counter_load\ \UART:BUART:rx_counter_load\/q \UART:BUART:sRX:RxBitCounter\/load 2.312
count7cell U(0,1) 1 \UART:BUART:sRX:RxBitCounter\ SETUP 4.220
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyHFCLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 45.325 MHz 22.063 19.604
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_postpoll\/main_1 6.609
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ SETUP 5.210
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_3 70.522 MHz 14.180 27.487
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:pollcount_1\/main_3 6.623
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_0\/main_2 70.592 MHz 14.166 27.501
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:pollcount_0\/main_2 6.609
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 76.138 MHz 13.134 28.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_last\/main_0 5.577
macrocell24 U(1,1) 1 \UART:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_9 76.144 MHz 13.133 28.534
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_state_0\/main_9 5.576
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_2\/main_8 76.764 MHz 13.027 28.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_state_2\/main_8 5.470
macrocell18 U(0,1) 1 \UART:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_6 76.764 MHz 13.027 28.640
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 4.047
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_status_3\/main_6 5.470
macrocell23 U(0,1) 1 \UART:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\UART:BUART:txn\/q \UART:BUART:txn\/main_0 3.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
macrocell9 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/q \UART:BUART:txn\/main_0 2.252
macrocell9 U(1,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 3.551
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell24 U(1,1) 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/clock_0 \UART:BUART:rx_last\/q 1.250
Route 1 \UART:BUART:rx_last\ \UART:BUART:rx_last\/q \UART:BUART:rx_state_2\/main_9 2.301
macrocell18 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 3.674
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_2\/main_4 2.674
macrocell12 U(1,0) 1 \UART:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 3.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:txn\/main_5 2.690
macrocell9 U(1,0) 1 \UART:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 3.690
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,0) 1 \UART:BUART:sTX:sCLOCK:TxBitClkGen\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 1.000
Route 1 \UART:BUART:tx_counter_dp\ \UART:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART:BUART:tx_state_1\/main_4 2.690
macrocell10 U(1,0) 1 \UART:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 3.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
Route 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_1\/main_4 2.539
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 3.790
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/clock_0 \UART:BUART:pollcount_0\/q 1.250
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ \UART:BUART:pollcount_0\/q \UART:BUART:pollcount_0\/main_3 2.540
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 4.051
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell16 U(0,1) 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/clock_0 \UART:BUART:rx_load_fifo\/q 1.250
Route 1 \UART:BUART:rx_load_fifo\ \UART:BUART:rx_load_fifo\/q \UART:BUART:sRX:RxShifter:u0\/f0_load 2.801
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 4.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_state_0\/main_4 2.820
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 4.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(0,1) 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/clock_0 \UART:BUART:rx_state_2\/q 1.250
Route 1 \UART:BUART:rx_state_2\ \UART:BUART:rx_state_2\/q \UART:BUART:rx_load_fifo\/main_4 2.820
macrocell16 U(0,1) 1 \UART:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx(0)/fb \UART:BUART:rx_state_2\/main_8 8.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_state_2\/main_8 5.470
macrocell18 U(0,1) 1 \UART:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_status_3\/main_6 8.210
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_status_3\/main_6 5.470
macrocell23 U(0,1) 1 \UART:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_state_0\/main_9 8.316
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_state_0\/main_9 5.576
macrocell15 U(0,1) 1 \UART:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:rx_last\/main_0 8.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_last\/main_0 5.577
macrocell24 U(1,1) 1 \UART:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_0\/main_2 9.349
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:pollcount_0\/main_2 6.609
macrocell22 U(0,0) 1 \UART:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:pollcount_1\/main_3 9.363
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:pollcount_1\/main_3 6.623
macrocell21 U(0,0) 1 \UART:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx(0)/fb \UART:BUART:sRX:RxShifter:u0\/route_si 15.546
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P0[4] 1 Rx(0) Rx(0)/in_clock Rx(0)/fb 2.740
Route 1 Net_342 Rx(0)/fb \UART:BUART:rx_postpoll\/main_1 6.609
macrocell6 U(0,0) 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/main_1 \UART:BUART:rx_postpoll\/q 3.350
Route 1 \UART:BUART:rx_postpoll\ \UART:BUART:rx_postpoll\/q \UART:BUART:sRX:RxShifter:u0\/route_si 2.847
datapathcell3 U(0,1) 1 \UART:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ Clock
Source Destination Delay (ns)
\UART:BUART:txn\/q Tx(0)_PAD 27.825
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(1,0) 1 \UART:BUART:txn\ \UART:BUART:txn\/clock_0 \UART:BUART:txn\/q 1.250
Route 1 \UART:BUART:txn\ \UART:BUART:txn\/q Net_337/main_0 3.171
macrocell1 U(1,1) 1 Net_337 Net_337/main_0 Net_337/q 3.350
Route 1 Net_337 Net_337/q Tx(0)/pin_input 5.444
iocell4 P0[5] 1 Tx(0) Tx(0)/pin_input Tx(0)/pad_out 14.610
Route 1 Tx(0)_PAD Tx(0)/pad_out Tx(0)_PAD 0.000
Clock Clock path delay 0.000