Static Timing Analysis

Project : Design01
Build Time : 11/06/15 03:13:06
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 32.787 kHz 32.787 kHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 32.787 kHz 32.787 kHz N/A
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
CyXTAL_32kHz CyXTAL_32kHz 32.768 kHz 32.768 kHz N/A
+ Clock To Output Section
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\I2C:I2C_FF\/scl_out Pin_2(0)_PAD:out 24.742
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/scl_out 1.000
Route 1 \I2C:Net_643_0\ \I2C:I2C_FF\/scl_out Pin_2(0)/pin_input 7.887
iocell2 P12[0] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 15.855
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C:I2C_FF\/sda_out Pin_1(0)_PAD:out 24.668
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C:I2C_FF\ \I2C:I2C_FF\/clock \I2C:I2C_FF\/sda_out 1.000
Route 1 \I2C:sda_x_wire\ \I2C:I2C_FF\/sda_out Pin_1(0)/pin_input 7.735
iocell1 P12[1] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 15.933
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD:out 0.000
Clock Clock path delay 0.000