Static Timing Analysis

Project : Digital_Pins01
Build Time : 10/11/18 09:10:45
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
Clock_1 CyMASTER_CLK 12.000 MHz 12.000 MHz 90.506 MHz
I2CM_IntClock CyMASTER_CLK 1.600 MHz 1.600 MHz 24.283 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyScBoostClk CyScBoostClk 12.000 MHz 12.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:genblk8:stsreg\/status_2 90.506 MHz 11.049 72.284
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_1:PWMUDB:tc_i\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:status_2\/main_1 2.596
macrocell9 U(2,2) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_1 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell2 U(2,2) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 91.483 MHz 10.931 72.402
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.581
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 100.040 MHz 9.996 73.337
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:status_2\/main_0 2.583
macrocell9 U(2,2) 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/main_0 \PWM_1:PWMUDB:status_2\/q 3.350
Route 1 \PWM_1:PWMUDB:status_2\ \PWM_1:PWMUDB:status_2\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_2 2.313
statusicell2 U(2,2) 1 \PWM_1:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 100.949 MHz 9.906 73.427
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.596
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_661/main_1 115.996 MHz 8.621 74.712
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_661/main_1 2.601
macrocell40 U(2,2) 1 Net_661 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 116.117 MHz 8.612 74.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.592
macrocell35 U(2,2) 1 \PWM_1:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 116.117 MHz 8.612 74.721
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.592
macrocell37 U(2,2) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 131.234 MHz 7.620 75.713
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.900
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_661/main_0 136.184 MHz 7.343 75.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_661/main_0 2.583
macrocell40 U(2,2) 1 Net_661 SETUP 3.510
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 141.844 MHz 7.050 76.283
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,2) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.290
macrocell37 U(2,2) 1 \PWM_1:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 625ns(1.6 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\I2CM:Net_643_3\/q \I2CM:bI2C_UDB:scl_in_reg\/main_0 24.283 MHz 41.181 583.819
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,1) 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/clock_0 \I2CM:Net_643_3\/q 1.250
Route 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/q I2CM_SCL(0)/pin_input 7.645
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pin_input I2CM_SCL(0)/pad_out 15.802
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pad_out I2CM_SCL(0)/pad_in 0.000
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pad_in I2CM_SCL(0)/fb 7.962
Route 1 \I2CM:Net_1109_0\ I2CM_SCL(0)/fb \I2CM:bI2C_UDB:scl_in_reg\/main_0 5.012
macrocell20 U(2,4) 1 \I2CM:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Skew 0.000
\I2CM:Net_643_3\/q \I2CM:bI2C_UDB:clk_eq_reg\/main_0 24.293 MHz 41.164 583.836
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,1) 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/clock_0 \I2CM:Net_643_3\/q 1.250
Route 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/q I2CM_SCL(0)/pin_input 7.645
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pin_input I2CM_SCL(0)/pad_out 15.802
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pad_out I2CM_SCL(0)/pad_in 0.000
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pad_in I2CM_SCL(0)/fb 7.962
Route 1 \I2CM:Net_1109_0\ I2CM_SCL(0)/fb \I2CM:bI2C_UDB:clk_eq_reg\/main_0 4.995
macrocell30 U(2,4) 1 \I2CM:bI2C_UDB:clk_eq_reg\ SETUP 3.510
Clock Skew 0.000
\I2CM:sda_x_wire\/q \I2CM:bI2C_UDB:status_1\/main_6 24.447 MHz 40.905 584.095
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,3) 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/clock_0 \I2CM:sda_x_wire\/q 1.250
Route 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/q I2CM_SDA(0)/pin_input 5.926
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pin_input I2CM_SDA(0)/pad_out 16.196
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pad_out I2CM_SDA(0)/pad_in 0.000
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pad_in I2CM_SDA(0)/fb 8.430
Route 1 \I2CM:Net_1109_1\ I2CM_SDA(0)/fb \I2CM:bI2C_UDB:status_1\/main_6 5.593
macrocell18 U(3,4) 1 \I2CM:bI2C_UDB:status_1\ SETUP 3.510
Clock Skew 0.000
\I2CM:sda_x_wire\/q \I2CM:bI2C_UDB:sda_in_reg\/main_0 24.996 MHz 40.006 584.994
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,3) 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/clock_0 \I2CM:sda_x_wire\/q 1.250
Route 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/q I2CM_SDA(0)/pin_input 5.926
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pin_input I2CM_SDA(0)/pad_out 16.196
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pad_out I2CM_SDA(0)/pad_in 0.000
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pad_in I2CM_SDA(0)/fb 8.430
Route 1 \I2CM:Net_1109_1\ I2CM_SDA(0)/fb \I2CM:bI2C_UDB:sda_in_reg\/main_0 4.694
macrocell10 U(2,3) 1 \I2CM:bI2C_UDB:sda_in_reg\ SETUP 3.510
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_3\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 34.949 MHz 28.613 596.387
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,5) 1 \I2CM:bI2C_UDB:m_state_3\ \I2CM:bI2C_UDB:m_state_3\/clock_0 \I2CM:bI2C_UDB:m_state_3\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_3\ \I2CM:bI2C_UDB:m_state_3\/q \I2CM:bI2C_UDB:cnt_reset\/main_1 9.093
macrocell4 U(2,3) 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/main_1 \I2CM:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/q \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 3.236
macrocell8 U(2,2) 1 \I2CM:bI2C_UDB:cs_addr_shifter_0\ \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2CM:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_shifter_0\ \I2CM:bI2C_UDB:cs_addr_shifter_0\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 2.324
datapathcell1 U(3,2) 1 \I2CM:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_3\/q \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 35.592 MHz 28.096 596.904
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(3,5) 1 \I2CM:bI2C_UDB:m_state_3\ \I2CM:bI2C_UDB:m_state_3\/clock_0 \I2CM:bI2C_UDB:m_state_3\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_3\ \I2CM:bI2C_UDB:m_state_3\/q \I2CM:bI2C_UDB:cnt_reset\/main_1 9.093
macrocell4 U(2,3) 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/main_1 \I2CM:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/q \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 4.631
macrocell5 U(2,1) 1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\ \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\ \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.292
datapathcell2 U(2,1) 1 \I2CM:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 36.674 MHz 27.267 597.733
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,3) 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/clock_0 \I2CM:bI2C_UDB:m_state_4\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:cnt_reset\/main_0 7.747
macrocell4 U(2,3) 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/main_0 \I2CM:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/q \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 3.236
macrocell8 U(2,2) 1 \I2CM:bI2C_UDB:cs_addr_shifter_0\ \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 \I2CM:bI2C_UDB:cs_addr_shifter_0\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_shifter_0\ \I2CM:bI2C_UDB:cs_addr_shifter_0\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 2.324
datapathcell1 U(3,2) 1 \I2CM:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_1 36.796 MHz 27.177 597.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,3) 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/clock_0 \I2CM:bI2C_UDB:m_state_4\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:cs_addr_shifter_1\/main_1 11.862
macrocell7 U(3,5) 1 \I2CM:bI2C_UDB:cs_addr_shifter_1\ \I2CM:bI2C_UDB:cs_addr_shifter_1\/main_1 \I2CM:bI2C_UDB:cs_addr_shifter_1\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_shifter_1\ \I2CM:bI2C_UDB:cs_addr_shifter_1\/q \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_1 4.705
datapathcell1 U(3,2) 1 \I2CM:bI2C_UDB:Shifter:u0\ SETUP 6.010
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 37.383 MHz 26.750 598.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,3) 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/clock_0 \I2CM:bI2C_UDB:m_state_4\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:cnt_reset\/main_0 7.747
macrocell4 U(2,3) 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/main_0 \I2CM:bI2C_UDB:cnt_reset\/q 3.350
Route 1 \I2CM:bI2C_UDB:cnt_reset\ \I2CM:bI2C_UDB:cnt_reset\/q \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 4.631
macrocell5 U(2,1) 1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\ \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_clkgen_1\ \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 2.292
datapathcell2 U(2,1) 1 \I2CM:bI2C_UDB:Master:ClkGen:u0\ SETUP 4.130
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:lost_arb_reg\/main_0 38.785 MHz 25.783 599.217
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(3,3) 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/clock_0 \I2CM:bI2C_UDB:m_state_4\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_4\ \I2CM:bI2C_UDB:m_state_4\/q \I2CM:bI2C_UDB:cs_addr_shifter_1\/main_1 11.862
macrocell7 U(3,5) 1 \I2CM:bI2C_UDB:cs_addr_shifter_1\ \I2CM:bI2C_UDB:cs_addr_shifter_1\/main_1 \I2CM:bI2C_UDB:cs_addr_shifter_1\/q 3.350
Route 1 \I2CM:bI2C_UDB:cs_addr_shifter_1\ \I2CM:bI2C_UDB:cs_addr_shifter_1\/q \I2CM:bI2C_UDB:lost_arb_reg\/main_0 5.811
macrocell26 U(3,1) 1 \I2CM:bI2C_UDB:lost_arb_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 1.573
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell37 U(2,2) 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/clock_0 \PWM_1:PWMUDB:status_0\/q 1.250
Route 1 \PWM_1:PWMUDB:status_0\ \PWM_1:PWMUDB:status_0\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_0 2.323
statusicell2 U(2,2) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 3.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,1) 1 \PWM_1:PWMUDB:genblk1:ctrlreg\ \PWM_1:PWMUDB:genblk1:ctrlreg\/clock \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 0.360
Route 1 \PWM_1:PWMUDB:control_7\ \PWM_1:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_1:PWMUDB:runmode_enable\/main_0 2.900
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 3.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:prevCompare1\/main_0 2.592
macrocell35 U(2,2) 1 \PWM_1:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 3.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_1:PWMUDB:status_0\/main_1 2.592
macrocell37 U(2,2) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_661/main_1 3.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/clock \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_1:PWMUDB:cmp1_less\ \PWM_1:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_661/main_1 2.601
macrocell40 U(2,2) 1 Net_661 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,5) 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/clock_0 \PWM_1:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare2\ \PWM_1:PWMUDB:prevCompare2\/q \PWM_1:PWMUDB:status_1\/main_0 2.288
macrocell38 U(2,5) 1 \PWM_1:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 3.540
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell35 U(2,2) 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/clock_0 \PWM_1:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_1:PWMUDB:prevCompare1\ \PWM_1:PWMUDB:prevCompare1\/q \PWM_1:PWMUDB:status_0\/main_0 2.290
macrocell37 U(2,2) 1 \PWM_1:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 3.643
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell38 U(2,5) 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/clock_0 \PWM_1:PWMUDB:status_1\/q 1.250
Route 1 \PWM_1:PWMUDB:status_1\ \PWM_1:PWMUDB:status_1\/q \PWM_1:PWMUDB:genblk8:stsreg\/status_1 4.393
statusicell2 U(2,2) 1 \PWM_1:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q Net_661/main_0 3.833
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q Net_661/main_0 2.583
macrocell40 U(2,2) 1 Net_661 HOLD 0.000
Clock Skew 0.000
\PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.846
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell34 U(2,2) 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/clock_0 \PWM_1:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_1:PWMUDB:runmode_enable\ \PWM_1:PWMUDB:runmode_enable\/q \PWM_1:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 2.596
datapathcell3 U(2,2) 1 \PWM_1:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2CM:bI2C_UDB:m_state_3\/main_2 2.685
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,5) 1 \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 0.360
Route 1 \I2CM:bI2C_UDB:control_2\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 \I2CM:bI2C_UDB:m_state_3\/main_2 2.325
macrocell12 U(3,5) 1 \I2CM:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \I2CM:bI2C_UDB:m_state_3\/main_1 2.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,5) 1 \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_5 0.360
Route 1 \I2CM:bI2C_UDB:control_5\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_5 \I2CM:bI2C_UDB:m_state_3\/main_1 2.638
macrocell12 U(3,5) 1 \I2CM:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \I2CM:bI2C_UDB:m_state_3\/main_0 3.031
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,5) 1 \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 0.360
Route 1 \I2CM:bI2C_UDB:control_6\ \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 \I2CM:bI2C_UDB:m_state_3\/main_0 2.671
macrocell12 U(3,5) 1 \I2CM:bI2C_UDB:m_state_3\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:sda_in_reg\/q \I2CM:bI2C_UDB:sda_in_last_reg\/main_0 3.554
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(2,3) 1 \I2CM:bI2C_UDB:sda_in_reg\ \I2CM:bI2C_UDB:sda_in_reg\/clock_0 \I2CM:bI2C_UDB:sda_in_reg\/q 1.250
Route 1 \I2CM:bI2C_UDB:sda_in_reg\ \I2CM:bI2C_UDB:sda_in_reg\/q \I2CM:bI2C_UDB:sda_in_last_reg\/main_0 2.304
macrocell23 U(2,3) 1 \I2CM:bI2C_UDB:sda_in_last_reg\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:bus_busy_reg\/q \I2CM:bI2C_UDB:bus_busy_reg\/main_6 3.569
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell29 U(2,4) 1 \I2CM:bI2C_UDB:bus_busy_reg\ \I2CM:bI2C_UDB:bus_busy_reg\/clock_0 \I2CM:bI2C_UDB:bus_busy_reg\/q 1.250
macrocell29 U(2,4) 1 \I2CM:bI2C_UDB:bus_busy_reg\ \I2CM:bI2C_UDB:bus_busy_reg\/q \I2CM:bI2C_UDB:bus_busy_reg\/main_6 2.319
macrocell29 U(2,4) 1 \I2CM:bI2C_UDB:bus_busy_reg\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:Shifter:u0\/so_comb \I2CM:sda_x_wire\/main_2 3.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(3,2) 1 \I2CM:bI2C_UDB:Shifter:u0\ \I2CM:bI2C_UDB:Shifter:u0\/clock \I2CM:bI2C_UDB:Shifter:u0\/so_comb 0.800
Route 1 \I2CM:bI2C_UDB:shift_data_out\ \I2CM:bI2C_UDB:Shifter:u0\/so_comb \I2CM:sda_x_wire\/main_2 2.897
macrocell32 U(3,3) 1 \I2CM:sda_x_wire\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_2\/q \I2CM:bI2C_UDB:m_state_2\/main_2 3.826
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \I2CM:bI2C_UDB:m_state_2\ \I2CM:bI2C_UDB:m_state_2\/clock_0 \I2CM:bI2C_UDB:m_state_2\/q 1.250
macrocell13 U(3,2) 1 \I2CM:bI2C_UDB:m_state_2\ \I2CM:bI2C_UDB:m_state_2\/q \I2CM:bI2C_UDB:m_state_2\/main_2 2.576
macrocell13 U(3,2) 1 \I2CM:bI2C_UDB:m_state_2\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:m_state_2\/q \I2CM:bI2C_UDB:m_state_0\/main_3 3.827
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell13 U(3,2) 1 \I2CM:bI2C_UDB:m_state_2\ \I2CM:bI2C_UDB:m_state_2\/clock_0 \I2CM:bI2C_UDB:m_state_2\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_state_2\ \I2CM:bI2C_UDB:m_state_2\/q \I2CM:bI2C_UDB:m_state_0\/main_3 2.577
macrocell15 U(3,2) 1 \I2CM:bI2C_UDB:m_state_0\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:m_reset\/q \I2CM:bI2C_UDB:m_state_0\/main_6 3.843
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,2) 1 \I2CM:bI2C_UDB:m_reset\ \I2CM:bI2C_UDB:m_reset\/clock_0 \I2CM:bI2C_UDB:m_reset\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_reset\ \I2CM:bI2C_UDB:m_reset\/q \I2CM:bI2C_UDB:m_state_0\/main_6 2.593
macrocell15 U(3,2) 1 \I2CM:bI2C_UDB:m_state_0\ HOLD 0.000
Clock Skew 0.000
\I2CM:bI2C_UDB:m_reset\/q \I2CM:bI2C_UDB:m_state_2\/main_3 3.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell33 U(3,2) 1 \I2CM:bI2C_UDB:m_reset\ \I2CM:bI2C_UDB:m_reset\/clock_0 \I2CM:bI2C_UDB:m_reset\/q 1.250
Route 1 \I2CM:bI2C_UDB:m_reset\ \I2CM:bI2C_UDB:m_reset\/q \I2CM:bI2C_UDB:m_state_2\/main_3 2.598
macrocell13 U(3,2) 1 \I2CM:bI2C_UDB:m_state_2\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ I2CM_IntClock
Source Destination Delay (ns)
I2CM_SDA(0)_PAD:in \I2CM:bI2C_UDB:status_1\/main_6 17.533
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 I2CM_SDA(0)_PAD I2CM_SDA(0)_PAD:in I2CM_SDA(0)/pad_in 0.000
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pad_in I2CM_SDA(0)/fb 8.430
Route 1 \I2CM:Net_1109_1\ I2CM_SDA(0)/fb \I2CM:bI2C_UDB:status_1\/main_6 5.593
macrocell18 U(3,4) 1 \I2CM:bI2C_UDB:status_1\ SETUP 3.510
Clock Clock path delay 0.000
I2CM_SCL(0)_PAD:in \I2CM:bI2C_UDB:scl_in_reg\/main_0 16.484
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 I2CM_SCL(0)_PAD I2CM_SCL(0)_PAD:in I2CM_SCL(0)/pad_in 0.000
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pad_in I2CM_SCL(0)/fb 7.962
Route 1 \I2CM:Net_1109_0\ I2CM_SCL(0)/fb \I2CM:bI2C_UDB:scl_in_reg\/main_0 5.012
macrocell20 U(2,4) 1 \I2CM:bI2C_UDB:scl_in_reg\ SETUP 3.510
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_1
Source Destination Delay (ns)
Net_661/q OutputPinSW(0)_PAD 25.304
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(2,2) 1 Net_661 Net_661/clock_0 Net_661/q 1.250
Route 1 Net_661 Net_661/q OutputPinSW(0)/pin_input 8.163
iocell1 P2[1] 1 OutputPinSW(0) OutputPinSW(0)/pin_input OutputPinSW(0)/pad_out 15.891
Route 1 OutputPinSW(0)_PAD OutputPinSW(0)/pad_out OutputPinSW(0)_PAD 0.000
Clock Clock path delay 0.000
+ I2CM_IntClock
Source Destination Delay (ns)
\I2CM:Net_643_3\/q I2CM_SCL(0)_PAD:out 24.697
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell31 U(2,1) 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/clock_0 \I2CM:Net_643_3\/q 1.250
Route 1 \I2CM:Net_643_3\ \I2CM:Net_643_3\/q I2CM_SCL(0)/pin_input 7.645
iocell2 P0[1] 1 I2CM_SCL(0) I2CM_SCL(0)/pin_input I2CM_SCL(0)/pad_out 15.802
Route 1 I2CM_SCL(0)_PAD I2CM_SCL(0)/pad_out I2CM_SCL(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2CM:sda_x_wire\/q I2CM_SDA(0)_PAD:out 23.372
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,3) 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/clock_0 \I2CM:sda_x_wire\/q 1.250
Route 1 \I2CM:sda_x_wire\ \I2CM:sda_x_wire\/q I2CM_SDA(0)/pin_input 5.926
iocell3 P12[3] 1 I2CM_SDA(0) I2CM_SDA(0)/pin_input I2CM_SDA(0)/pad_out 16.196
Route 1 I2CM_SDA(0)_PAD I2CM_SDA(0)/pad_out I2CM_SDA(0)_PAD:out 0.000
Clock Clock path delay 0.000