# Static Timing Analysis

Project : | Digital_Pins01
Build Time : | 10/04/18 14:10:05
Device : | CY8C5888LTI-LP097
Temperature : | -40C - 85/125C
VDDA : | 3.30
VDDABUF : | 3.30
VDDD : | 3.30
VDDIO0 : | 3.30
VDDIO1 : | 3.30
VDDIO2 : | 3.30
VDDIO3 : | 3.30
VUSB : | 3.30
Voltage : | 3.3

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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section

Clock | Domain | Nominal Frequency | Required Frequency | Maximum Frequency | Violation
--- | --- | --- | --- | --- | ---
CyILO | CyILO | 1.000 kHz | 1.000 kHz | N/A |
CyIMO | CyIMO | 3.000 MHz | 3.000 MHz | N/A |
CyMASTER_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
CyBUS_CLK | CyMASTER_CLK | 24.000 MHz | 24.000 MHz | N/A |
Clock_1 | CyMASTER_CLK | 1.000 MHz | 1.000 MHz | 25.154 MHz |
CyPLL_OUT | CyPLL_OUT | 24.000 MHz | 24.000 MHz | N/A |
CyScBoostClk | CyScBoostClk | 12.000 MHz | 12.000 MHz | N/A |

+ Register to Register Section
+ Setup Subsection
+ Source Clock : Clock_1 : Positive edge(Required Frequency 1 MHz)
+ Destination Clock : Clock_1 : Positive edge(Required Frequency 1 MHz)
Path Delay Requirement : 1000ns(1 MHz)

Source | Destination | FMax | Delay (ns) | Slack (ns) | Violation
--- | --- | --- | --- | --- | ---
\I2CM:sda_x_wire\/q | \I2CM:bI2C_UDB:status_1\/main_6 | 25.154 MHz | 39.755 | 960.245 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell32 | U(3,0) | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/clock_0 | \I2CM:sda_x_wire\/q | 1.250
Route |  | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/q | SDA(0)/pin_input | 5.770
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pin_input | SDA(0)/pad_out | 15.933
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pad_out | SDA(0)/pad_in | 0.000
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pad_in | SDA(0)/fb | 7.630
Route |  | 1 | \I2CM:Net_1109_1\ | SDA(0)/fb | \I2CM:bI2C_UDB:status_1\/main_6 | 5.662
macrocell18 | U(2,1) | 1 | \I2CM:bI2C_UDB:status_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\I2CM:Net_643_3\/q | \I2CM:bI2C_UDB:scl_in_reg\/main_0 | 25.221 MHz | 39.650 | 960.350 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell31 | U(2,0) | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/clock_0 | \I2CM:Net_643_3\/q | 1.250
Route |  | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/q | SCL(0)/pin_input | 5.780
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pin_input | SCL(0)/pad_out | 15.855
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pad_out | SCL(0)/pad_in | 0.000
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pad_in | SCL(0)/fb | 6.830
Route |  | 1 | \I2CM:Net_1109_0\ | SCL(0)/fb | \I2CM:bI2C_UDB:scl_in_reg\/main_0 | 6.425
macrocell20 | U(2,2) | 1 | \I2CM:bI2C_UDB:scl_in_reg\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\I2CM:sda_x_wire\/q | \I2CM:bI2C_UDB:sda_in_reg\/main_0 | 25.620 MHz | 39.032 | 960.968 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell32 | U(3,0) | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/clock_0 | \I2CM:sda_x_wire\/q | 1.250
Route |  | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/q | SDA(0)/pin_input | 5.770
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pin_input | SDA(0)/pad_out | 15.933
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pad_out | SDA(0)/pad_in | 0.000
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pad_in | SDA(0)/fb | 7.630
Route |  | 1 | \I2CM:Net_1109_1\ | SDA(0)/fb | \I2CM:bI2C_UDB:sda_in_reg\/main_0 | 4.939
macrocell10 | U(2,0) | 1 | \I2CM:bI2C_UDB:sda_in_reg\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\I2CM:Net_643_3\/q | \I2CM:bI2C_UDB:clk_eq_reg\/main_0 | 26.186 MHz | 38.189 | 961.811 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell31 | U(2,0) | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/clock_0 | \I2CM:Net_643_3\/q | 1.250
Route |  | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/q | SCL(0)/pin_input | 5.780
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pin_input | SCL(0)/pad_out | 15.855
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pad_out | SCL(0)/pad_in | 0.000
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pad_in | SCL(0)/fb | 6.830
Route |  | 1 | \I2CM:Net_1109_0\ | SCL(0)/fb | \I2CM:bI2C_UDB:clk_eq_reg\/main_0 | 4.964
macrocell30 | U(3,0) | 1 | \I2CM:bI2C_UDB:clk_eq_reg\ |  | SETUP | 3.510
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:m_state_3\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 36.617 MHz | 27.310 | 972.690 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell12 | U(3,3) | 1 | \I2CM:bI2C_UDB:m_state_3\ | \I2CM:bI2C_UDB:m_state_3\/clock_0 | \I2CM:bI2C_UDB:m_state_3\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:m_state_3\ | \I2CM:bI2C_UDB:m_state_3\/q | \I2CM:bI2C_UDB:cnt_reset\/main_1 | 7.379
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_1 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | 2.306
macrocell8 | U(3,1) | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 3.665
datapathcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:Shifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:m_state_1\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 39.502 MHz | 25.315 | 974.685 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell14 | U(2,2) | 1 | \I2CM:bI2C_UDB:m_state_1\ | \I2CM:bI2C_UDB:m_state_1\/clock_0 | \I2CM:bI2C_UDB:m_state_1\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:m_state_1\ | \I2CM:bI2C_UDB:m_state_1\/q | \I2CM:bI2C_UDB:cnt_reset\/main_3 | 5.384
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_3 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | 2.306
macrocell8 | U(3,1) | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 3.665
datapathcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:Shifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:m_state_3\/q | \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 | 39.890 MHz | 25.069 | 974.931 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell12 | U(3,3) | 1 | \I2CM:bI2C_UDB:m_state_3\ | \I2CM:bI2C_UDB:m_state_3\/clock_0 | \I2CM:bI2C_UDB:m_state_3\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:m_state_3\ | \I2CM:bI2C_UDB:m_state_3\/q | \I2CM:bI2C_UDB:cnt_reset\/main_1 | 7.379
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_1 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 | 3.361
macrocell5 | U(2,0) | 1 | \I2CM:bI2C_UDB:cs_addr_clkgen_1\ | \I2CM:bI2C_UDB:cs_addr_clkgen_1\/main_1 | \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_clkgen_1\ | \I2CM:bI2C_UDB:cs_addr_clkgen_1\/q | \I2CM:bI2C_UDB:Master:ClkGen:u0\/cs_addr_1 | 2.249
datapathcell2 | U(2,0) | 1 | \I2CM:bI2C_UDB:Master:ClkGen:u0\ |  | SETUP | 4.130
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:m_state_2\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 40.463 MHz | 24.714 | 975.286 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell13 | U(3,0) | 1 | \I2CM:bI2C_UDB:m_state_2\ | \I2CM:bI2C_UDB:m_state_2\/clock_0 | \I2CM:bI2C_UDB:m_state_2\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:m_state_2\ | \I2CM:bI2C_UDB:m_state_2\/q | \I2CM:bI2C_UDB:cnt_reset\/main_2 | 4.783
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_2 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | 2.306
macrocell8 | U(3,1) | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 3.665
datapathcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:Shifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:clkgen_tc1_reg\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 40.510 MHz | 24.685 | 975.315 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell25 | U(2,0) | 1 | \I2CM:bI2C_UDB:clkgen_tc1_reg\ | \I2CM:bI2C_UDB:clkgen_tc1_reg\/clock_0 | \I2CM:bI2C_UDB:clkgen_tc1_reg\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:clkgen_tc1_reg\ | \I2CM:bI2C_UDB:clkgen_tc1_reg\/q | \I2CM:bI2C_UDB:cnt_reset\/main_7 | 4.754
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_7 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | 2.306
macrocell8 | U(3,1) | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 3.665
datapathcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:Shifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:m_state_4\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 41.415 MHz | 24.146 | 975.854 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell11 | U(3,0) | 1 | \I2CM:bI2C_UDB:m_state_4\ | \I2CM:bI2C_UDB:m_state_4\/clock_0 | \I2CM:bI2C_UDB:m_state_4\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:m_state_4\ | \I2CM:bI2C_UDB:m_state_4\/q | \I2CM:bI2C_UDB:cnt_reset\/main_0 | 4.215
macrocell4 | U(2,1) | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/main_0 | \I2CM:bI2C_UDB:cnt_reset\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cnt_reset\ | \I2CM:bI2C_UDB:cnt_reset\/q | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | 2.306
macrocell8 | U(3,1) | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/main_3 | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | 3.350
Route |  | 1 | \I2CM:bI2C_UDB:cs_addr_shifter_0\ | \I2CM:bI2C_UDB:cs_addr_shifter_0\/q | \I2CM:bI2C_UDB:Shifter:u0\/cs_addr_0 | 3.665
datapathcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:Shifter:u0\ |  | SETUP | 6.010
Clock |  |  |  |  | Skew | 0.000

+ Hold Subsection
+ Source Clock : Clock_1 : Positive edge
+ Destination Clock : Clock_1 : Positive edge

Source | Destination | Slack (ns) | Violation
--- | --- | --- | ---
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_1 | \I2CM:bI2C_UDB:m_reset\/main_0 | 2.696 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_1 | 0.360
Route |  | 1 | \I2CM:bI2C_UDB:control_1\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_1 | \I2CM:bI2C_UDB:m_reset\/main_0 | 2.336
macrocell33 | U(2,3) | 1 | \I2CM:bI2C_UDB:m_reset\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 | \I2CM:bI2C_UDB:m_state_3\/main_0 | 2.978 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 | 0.360
Route |  | 1 | \I2CM:bI2C_UDB:control_6\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_6 | \I2CM:bI2C_UDB:m_state_3\/main_0 | 2.618
macrocell12 | U(3,3) | 1 | \I2CM:bI2C_UDB:m_state_3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 | \I2CM:bI2C_UDB:m_state_3\/main_2 | 2.999 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
controlcell1 | U(3,3) | 1 | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/clock | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 | 0.360
Route |  | 1 | \I2CM:bI2C_UDB:control_2\ | \I2CM:bI2C_UDB:SyncCtl:CtrlReg\/control_2 | \I2CM:bI2C_UDB:m_state_3\/main_2 | 2.639
macrocell12 | U(3,3) | 1 | \I2CM:bI2C_UDB:m_state_3\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:bus_busy_reg\/q | \I2CM:bI2C_UDB:bus_busy_reg\/main_6 | 3.546 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell29 | U(2,1) | 1 | \I2CM:bI2C_UDB:bus_busy_reg\ | \I2CM:bI2C_UDB:bus_busy_reg\/clock_0 | \I2CM:bI2C_UDB:bus_busy_reg\/q | 1.250
macrocell29 | U(2,1) | 1 | \I2CM:bI2C_UDB:bus_busy_reg\ | \I2CM:bI2C_UDB:bus_busy_reg\/q | \I2CM:bI2C_UDB:bus_busy_reg\/main_6 | 2.296
macrocell29 | U(2,1) | 1 | \I2CM:bI2C_UDB:bus_busy_reg\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:status_0\/q | \I2CM:bI2C_UDB:status_0\/main_0 | 3.547 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell19 | U(2,2) | 1 | \I2CM:bI2C_UDB:status_0\ | \I2CM:bI2C_UDB:status_0\/clock_0 | \I2CM:bI2C_UDB:status_0\/q | 1.250
macrocell19 | U(2,2) | 1 | \I2CM:bI2C_UDB:status_0\ | \I2CM:bI2C_UDB:status_0\/q | \I2CM:bI2C_UDB:status_0\/main_0 | 2.297
macrocell19 | U(2,2) | 1 | \I2CM:bI2C_UDB:status_0\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:scl_in_last2_reg\/q | \I2CM:bI2C_UDB:bus_busy_reg\/main_2 | 3.551 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell22 | U(2,1) | 1 | \I2CM:bI2C_UDB:scl_in_last2_reg\ | \I2CM:bI2C_UDB:scl_in_last2_reg\/clock_0 | \I2CM:bI2C_UDB:scl_in_last2_reg\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:scl_in_last2_reg\ | \I2CM:bI2C_UDB:scl_in_last2_reg\/q | \I2CM:bI2C_UDB:bus_busy_reg\/main_2 | 2.301
macrocell29 | U(2,1) | 1 | \I2CM:bI2C_UDB:bus_busy_reg\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:lost_arb_reg\/q | \I2CM:bI2C_UDB:lost_arb_reg\/main_2 | 3.789 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell26 | U(3,0) | 1 | \I2CM:bI2C_UDB:lost_arb_reg\ | \I2CM:bI2C_UDB:lost_arb_reg\/clock_0 | \I2CM:bI2C_UDB:lost_arb_reg\/q | 1.250
macrocell26 | U(3,0) | 1 | \I2CM:bI2C_UDB:lost_arb_reg\ | \I2CM:bI2C_UDB:lost_arb_reg\/q | \I2CM:bI2C_UDB:lost_arb_reg\/main_2 | 2.539
macrocell26 | U(3,0) | 1 | \I2CM:bI2C_UDB:lost_arb_reg\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:sda_in_reg\/q | \I2CM:bI2C_UDB:sda_in_last_reg\/main_0 | 3.791 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell10 | U(2,0) | 1 | \I2CM:bI2C_UDB:sda_in_reg\ | \I2CM:bI2C_UDB:sda_in_reg\/clock_0 | \I2CM:bI2C_UDB:sda_in_reg\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:sda_in_reg\ | \I2CM:bI2C_UDB:sda_in_reg\/q | \I2CM:bI2C_UDB:sda_in_last_reg\/main_0 | 2.541
macrocell23 | U(2,0) | 1 | \I2CM:bI2C_UDB:sda_in_last_reg\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:lost_arb_reg\/q | \I2CM:sda_x_wire\/main_9 | 3.793 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell26 | U(3,0) | 1 | \I2CM:bI2C_UDB:lost_arb_reg\ | \I2CM:bI2C_UDB:lost_arb_reg\/clock_0 | \I2CM:bI2C_UDB:lost_arb_reg\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:lost_arb_reg\ | \I2CM:bI2C_UDB:lost_arb_reg\/q | \I2CM:sda_x_wire\/main_9 | 2.543
macrocell32 | U(3,0) | 1 | \I2CM:sda_x_wire\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000
\I2CM:bI2C_UDB:clkgen_tc1_reg\/q | \I2CM:bI2C_UDB:m_state_2\/main_4 | 3.794 |
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell25 | U(2,0) | 1 | \I2CM:bI2C_UDB:clkgen_tc1_reg\ | \I2CM:bI2C_UDB:clkgen_tc1_reg\/clock_0 | \I2CM:bI2C_UDB:clkgen_tc1_reg\/q | 1.250
Route |  | 1 | \I2CM:bI2C_UDB:clkgen_tc1_reg\ | \I2CM:bI2C_UDB:clkgen_tc1_reg\/q | \I2CM:bI2C_UDB:m_state_2\/main_4 | 2.544
macrocell13 | U(3,0) | 1 | \I2CM:bI2C_UDB:m_state_2\ |  | HOLD | 0.000
Clock |  |  |  |  | Skew | 0.000

+ Input To Clock Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
SDA(0)_PAD:in | \I2CM:bI2C_UDB:status_1\/main_6 | 16.802
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
Route |  | 1 | SDA(0)_PAD | SDA(0)_PAD:in | SDA(0)/pad_in | 0.000
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pad_in | SDA(0)/fb | 7.630
Route |  | 1 | \I2CM:Net_1109_1\ | SDA(0)/fb | \I2CM:bI2C_UDB:status_1\/main_6 | 5.662
macrocell18 | U(2,1) | 1 | \I2CM:bI2C_UDB:status_1\ |  | SETUP | 3.510
Clock |  |  |  |  | Clock path delay | 0.000
SCL(0)_PAD:in | \I2CM:bI2C_UDB:scl_in_reg\/main_0 | 16.765
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
Route |  | 1 | SCL(0)_PAD | SCL(0)_PAD:in | SCL(0)/pad_in | 0.000
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pad_in | SCL(0)/fb | 6.830
Route |  | 1 | \I2CM:Net_1109_0\ | SCL(0)/fb | \I2CM:bI2C_UDB:scl_in_reg\/main_0 | 6.425
macrocell20 | U(2,2) | 1 | \I2CM:bI2C_UDB:scl_in_reg\ |  | SETUP | 3.510
Clock |  |  |  |  | Clock path delay | 0.000

+ Clock To Output Section
+ Clock_1

Source | Destination | Delay (ns)
--- | --- | ---
\I2CM:sda_x_wire\/q | SDA(0)_PAD:out | 22.953
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell32 | U(3,0) | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/clock_0 | \I2CM:sda_x_wire\/q | 1.250
Route |  | 1 | \I2CM:sda_x_wire\ | \I2CM:sda_x_wire\/q | SDA(0)/pin_input | 5.770
iocell3 | P12[1] | 1 | SDA(0) | SDA(0)/pin_input | SDA(0)/pad_out | 15.933
Route |  | 1 | SDA(0)_PAD | SDA(0)/pad_out | SDA(0)_PAD:out | 0.000
Clock |  |  |  |  | Clock path delay | 0.000
\I2CM:Net_643_3\/q | SCL(0)_PAD:out | 22.885
Type | Location | Fanout | Instance/Net | Source | Dest | Delay (ns)
--- | --- | --- | --- | --- | --- | ---
macrocell31 | U(2,0) | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/clock_0 | \I2CM:Net_643_3\/q | 1.250
Route |  | 1 | \I2CM:Net_643_3\ | \I2CM:Net_643_3\/q | SCL(0)/pin_input | 5.780
iocell2 | P12[0] | 1 | SCL(0) | SCL(0)/pin_input | SCL(0)/pad_out | 15.855
Route |  | 1 | SCL(0)_PAD | SCL(0)/pad_out | SCL(0)_PAD:out | 0.000
Clock |  |  |  |  | Clock path delay | 0.000