Static Timing Analysis

Project : MTK+TWI+RT
Build Time : 04/28/21 20:36:15
Device : CY8C6347LQI-BLD52
Temperature : -40C
VBACKUP : 1.80
VDDA : 1.80
VDDA_CSD : 1.80
VDDD : 1.80
VDDIO_0 : 1.80
VDDIO_0_RCV : 1.80
VDDIO_1 : 1.80
VDDIO_A : 1.80
VDDQ : 1.80
VDDR_HVL_2 : 1.80
VDDR_HVL_3 : 1.80
VDD_NS : 1.80
Voltage : 1.8
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyClk_Fast CyClk_Fast 50.000 MHz 50.000 MHz N/A
CyClk_HF0 CyClk_HF0 50.000 MHz 50.000 MHz N/A
CyClk_LF CyClk_LF 32.000 kHz 32.000 kHz N/A
CyClk_Peri CyClk_Peri 25.000 MHz 25.000 MHz N/A
CyClk_Slow CyClk_Peri 25.000 MHz 25.000 MHz N/A
MTK_SCBCLK CyClk_Peri 1.389 MHz 1.389 MHz N/A
UART_2_Wire_SCBCLK CyClk_Peri 1.389 MHz 1.389 MHz N/A
CyFLL CyFLL 50.000 MHz 50.000 MHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 8.000 MHz 8.000 MHz N/A
CyPeriClk_App CyPeriClk_App 25.000 MHz 25.000 MHz N/A