Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.4 (WebPack) - P.49d Target Family: Spartan6
OS Platform: NT Target Device: xc6slx25
Project ID (random number) e333ae5154d542c9a02c9b4e98c23735.9108E93BDDF040749F32ABBE977940E4.4 Target Package: ftg256
Registration ID __0_0_0 Target Speed: -3
Date Generated 2013-03-26T13:59:40 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Core(TM)2 Duo CPU T7500 @ 2.20GHz CPU Speed 2194 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Comparators=1
  • 4-bit comparator greater=1
Counters=1
  • 4-bit up counter=1
FSMs=1 Registers=1
  • Flip-Flops=1
MiscellaneousStatistics
  • AGG_BONDED_IO=27
  • AGG_IO=27
  • AGG_LOCED_IO=27
  • AGG_SLICE=5
  • NUM_BONDED_IOB=27
  • NUM_BSFULL=3
  • NUM_BSLUTONLY=3
  • NUM_BSREGONLY=1
  • NUM_BSUSED=7
  • NUM_BUFG=2
  • NUM_BUFIO2=1
  • NUM_BUFIO2FB=1
  • NUM_DCM=1
  • NUM_IOB_FF=1
  • NUM_LOCED_IOB=27
  • NUM_LOGIC_O5ANDO6=2
  • NUM_LOGIC_O6ONLY=4
  • NUM_OLOGIC2=1
  • NUM_SLICEX=5
  • NUM_SLICE_CONTROLSET=2
  • NUM_SLICE_CYINIT=8
  • NUM_SLICE_FF=6
  • NUM_SLICE_UNUSEDCTRL=2
  • NUM_UNUSABLE_FF_BELS=10
NetStatistics
  • NumNets_Active=63
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=1
  • NumNodesOfType_Active_BOUNCEIN=1
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=3
  • NumNodesOfType_Active_BUFIOINP=2
  • NumNodesOfType_Active_CLKPIN=5
  • NumNodesOfType_Active_CLKPINFEED=9
  • NumNodesOfType_Active_CNTRLPIN=4
  • NumNodesOfType_Active_DOUBLE=10
  • NumNodesOfType_Active_GENERIC=14
  • NumNodesOfType_Active_GLOBAL=18
  • NumNodesOfType_Active_INPUT=4
  • NumNodesOfType_Active_IOBIN2OUT=6
  • NumNodesOfType_Active_IOBOUTPUT=7
  • NumNodesOfType_Active_LUTINPUT=19
  • NumNodesOfType_Active_OUTBOUND=13
  • NumNodesOfType_Active_OUTPUT=18
  • NumNodesOfType_Active_PADINPUT=4
  • NumNodesOfType_Active_PADOUTPUT=2
  • NumNodesOfType_Active_PINBOUNCE=7
  • NumNodesOfType_Active_PINFEED=34
  • NumNodesOfType_Active_PINFEED1=1
  • NumNodesOfType_Active_PINFEED2=3
  • NumNodesOfType_Active_QUAD=35
  • NumNodesOfType_Active_REGINPUT=1
  • NumNodesOfType_Active_SINGLE=11
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_DOUBLE=1
  • NumNodesOfType_Gnd_GENERIC=3
  • NumNodesOfType_Gnd_HGNDOUT=2
  • NumNodesOfType_Gnd_IOBIN2OUT=3
  • NumNodesOfType_Gnd_IOBINPUT=1
  • NumNodesOfType_Gnd_IOBOUTPUT=3
  • NumNodesOfType_Gnd_OUTBOUND=5
  • NumNodesOfType_Gnd_OUTPUT=7
  • NumNodesOfType_Gnd_PADINPUT=3
  • NumNodesOfType_Gnd_PINFEED=8
  • NumNodesOfType_Gnd_SINGLE=4
  • NumNodesOfType_Vcc_CNTRLPIN=1
  • NumNodesOfType_Vcc_GENERIC=1
  • NumNodesOfType_Vcc_HVCCOUT=2
  • NumNodesOfType_Vcc_IOBIN2OUT=2
  • NumNodesOfType_Vcc_IOBOUTPUT=1
  • NumNodesOfType_Vcc_KVCCOUT=1
  • NumNodesOfType_Vcc_LUTINPUT=2
  • NumNodesOfType_Vcc_PADINPUT=1
  • NumNodesOfType_Vcc_PINFEED=5
SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=13
  • IOB-IOBS=14
  • SLICEX-SLICEL=4
SiteSummary
  • BUFG=2
  • BUFG_BUFG=2
  • BUFIO2=1
  • BUFIO2FB=1
  • BUFIO2FB_BUFIO2FB=1
  • BUFIO2_BUFIO2=1
  • DCM=1
  • DCM_DCM=1
  • FF_SR=2
  • IOB=27
  • IOB_IMUX=19
  • IOB_INBUF=19
  • IOB_OUTBUF=8
  • LUT5=2
  • LUT6=6
  • OLOGIC2=1
  • OLOGIC2_OUTFF=1
  • PAD=27
  • REG_SR=4
  • SLICEX=5
 
Configuration Data
BUFIO2FB_BUFIO2FB
  • DIVIDE_BYPASS=[TRUE:1]
  • INVERT_INPUTS=[FALSE:1]
BUFIO2_BUFIO2
  • DIVIDE=[1:1]
  • DIVIDE_BYPASS=[TRUE:1]
  • I_INVERT=[FALSE:1]
DCM
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2.0:1]
  • CLKIN_DIVIDE_BY_2=[FALSE:1]
  • CLKOUT_PHASE_SHIFT=[NONE:1]
  • CLK_FEEDBACK=[1X:1]
  • DESKEW_ADJUST=[5:1]
  • DFS_FREQUENCY_MODE=[LOW:1]
  • DLL_FREQUENCY_MODE=[LOW:1]
  • DSS_MODE=[NONE:1]
  • DUTY_CYCLE_CORRECTION=[TRUE:1]
  • PSCLK=[PSCLK_INV:0] [PSCLK:1]
  • PSEN=[PSEN_INV:0] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:0] [PSINCDEC:1]
  • RST=[RST:1] [RST_INV:0]
  • STARTUP_WAIT=[FALSE:1]
  • VERY_HIGH_FREQUENCY=[FALSE:1]
FF_SR
  • CK=[CK:2] [CK_INV:0]
  • SRINIT=[SRINIT0:2]
  • SYNC_ATTR=[ASYNC:2]
IOB_OUTBUF
  • DRIVEATTRBOX=[12:8]
  • SLEW=[SLOW:8]
  • SUSPEND=[3STATE:8]
OLOGIC2
  • CLK0=[CLK0_INV:0] [CLK0:1]
  • CLK1=[CLK1:0] [CLK1_INV:1]
OLOGIC2_OUTFF
  • CK0=[CK0_INV:0] [CK0:1]
  • CK1=[CK1_INV:1] [CK1:0]
  • DDR_ALIGNMENT=[NONE:1]
  • OUTFFTYPE=[DDR:1]
  • SRINIT_OQ=[0:1]
  • SRTYPE_OQ=[SYNC:1]
REG_SR
  • CK=[CK:4] [CK_INV:0]
  • LATCH_OR_FF=[FF:4]
  • SRINIT=[SRINIT0:4]
  • SYNC_ATTR=[ASYNC:4]
SLICEX
  • CLK=[CLK:3] [CLK_INV:0]
 
Pin Data
BUFG
  • I0=2
  • O=2
BUFG_BUFG
  • I0=2
  • O=2
BUFIO2
  • DIVCLK=1
  • I=1
BUFIO2FB
  • I=1
  • O=1
BUFIO2FB_BUFIO2FB
  • I=1
  • O=1
BUFIO2_BUFIO2
  • DIVCLK=1
  • I=1
DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
DCM_DCM
  • CLK0=1
  • CLK180=1
  • CLKFB=1
  • CLKIN=1
  • LOCKED=1
  • PSCLK=1
  • PSEN=1
  • PSINCDEC=1
  • RST=1
FF_SR
  • CK=2
  • D=2
  • Q=2
  • SR=2
IOB
  • I=19
  • O=8
  • PAD=27
IOB_IMUX
  • I=19
  • OUT=19
IOB_INBUF
  • OUT=19
  • PAD=19
IOB_OUTBUF
  • IN=8
  • OUT=8
LUT5
  • A1=1
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • O5=2
LUT6
  • A2=2
  • A3=3
  • A4=4
  • A5=5
  • A6=6
  • O6=6
OLOGIC2
  • CLK0=1
  • CLK1=1
  • D1=1
  • D2=1
  • OCE=1
  • OQ=1
  • SR=1
OLOGIC2_OUTFF
  • CE=1
  • CK0=1
  • CK1=1
  • D1=1
  • D2=1
  • Q=1
  • SR=1
PAD
  • PAD=27
REG_SR
  • CE=1
  • CK=4
  • D=4
  • Q=4
  • SR=4
SLICEX
  • A2=1
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • AMUX=1
  • AQ=3
  • AX=1
  • B1=1
  • B2=1
  • B3=1
  • B4=1
  • B5=1
  • B6=1
  • BMUX=1
  • BQ=1
  • C=1
  • C6=1
  • CE=1
  • CLK=3
  • D=2
  • D4=1
  • D5=2
  • D6=2
  • SR=3
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx25-ftg256-3 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx25-ftg256-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 6 5 0 0 0 0 0
bitgen 118 118 0 0 0 0 0
cse_server 55 55 0 0 0 0 0
map 120 118 0 0 0 0 0
ngcbuild 31 31 0 0 0 0 0
ngdbuild 127 127 0 0 0 0 0
par 118 118 0 0 0 0 0
trce 118 118 0 0 0 0 0
xst 235 233 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-03-15T12:19:53
PROP_intWbtProjectID=9108E93BDDF040749F32ABBE977940E4 PROP_intWbtProjectIteration=4
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_xilxBitgStart_IntDone=true PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx25
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=ftg256
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-3
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=2
 
Core Statistics
Core Type=clk_wiz_v3_6
clkin1_period=20.833 clkin2_period=20.833 clock_mgr_type=AUTO feedback_source=FDBK_AUTO
feedback_type=SINGLE manual_override=false num_out_clk=4 primtype_sel=DCM_SP
use_clk_valid=false use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false
use_inclk_stopped=false use_inclk_switchover=false use_locked=true use_max_i_jitter=false
use_min_o_jitter=false use_phase_alignment=true use_power_down=false use_reset=true
use_status=false
 
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_BUFG=1 XST_NUM_IBUFG=1 XST_NUM_ODDR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=5 NGDBUILD_NUM_FDCE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2
NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=4 NGDBUILD_NUM_LUT5=1
NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_VCC=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4 NGDBUILD_NUM_DCM_SP=1 NGDBUILD_NUM_FDC=5 NGDBUILD_NUM_FDCE=1
NGDBUILD_NUM_GND=1 NGDBUILD_NUM_IBUF=18 NGDBUILD_NUM_IBUFG=1 NGDBUILD_NUM_INV=2
NGDBUILD_NUM_LUT2=1 NGDBUILD_NUM_LUT3=1 NGDBUILD_NUM_LUT4=4 NGDBUILD_NUM_LUT5=1
NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_ODDR2=1 NGDBUILD_NUM_VCC=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ofn=<design_top> -ofmt=NGC -p=xc6slx25-3-ftg256
-top=<design_top> -opt_mode=Speed -opt_level=1 -power=NO
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -dsp_utilization_ratio=100
-reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No
-fsm_style=LUT -ram_extract=Yes -ram_style=Auto -rom_extract=Yes
-shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES
-async_to_sync=NO -use_dsp48=Auto -iobuf=YES -max_fanout=100000
-bufg=16 -register_duplication=YES -register_balancing=No -optimize_primitives=NO
-use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto -iob=Auto
-equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5