clk_wiz_v3_6 Project Status
Project File: fl2l_streamIN_vhdl_proj.xise Parser Errors: No Errors
Module Name: clk_wiz_v3_6 Implementation State: New
Target Device: xc6slx25-3ftg256
  • Errors:
 
Product Version:ISE 14.4
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Mar 13 15:41:57 2013
WebTalk Log FileCurrentWed Mar 13 15:42:06 2013

Date Generated: 03/13/2013 - 15:47:08