Static Timing Analysis

Project : Owl Ears
Build Time : 09/05/14 21:14:30
Device : CY8C5868LTI-LP039
Temperature : -40C - 85/125C
Vdda : 5.00
Vddd : 5.00
Vio0 : 5.00
Vio1 : 5.00
Vio2 : 5.00
Vio3 : 5.00
Voltage : 5.0
Vusb : 5.00
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_SAR_Seq_IntClock(routed) ADC_SAR_Seq_IntClock(routed) 2.182 MHz 2.182 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
ADC_SAR_Seq_IntClock CyMASTER_CLK 2.182 MHz 2.182 MHz 22.446 MHz
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 55.399 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 458.333ns(2.18182 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\/main_0 22.446 MHz 44.551 413.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\/main_0 19.023
macrocell22 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_20\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_31\/main_0 22.446 MHz 44.551 413.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_31\/main_0 19.023
macrocell34 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_31\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\/main_0 22.446 MHz 44.551 413.782
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\/main_0 19.023
macrocell61 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_56\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_2\/main_0 22.451 MHz 44.542 413.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_2\/main_0 19.014
macrocell32 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_2\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_55\/main_0 22.451 MHz 44.542 413.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_55\/main_0 19.014
macrocell60 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_55\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_9\/main_0 22.451 MHz 44.542 413.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_9\/main_0 19.014
macrocell73 U(3,4) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_9\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_49\/main_0 23.617 MHz 42.343 415.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_49\/main_0 16.815
macrocell53 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_49\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\/main_0 23.617 MHz 42.343 415.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\/main_0 16.815
macrocell62 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_57\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_33\/main_0 24.017 MHz 41.637 416.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_33\/main_0 16.109
macrocell36 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_33\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_3\/main_0 24.017 MHz 41.637 416.696
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(3,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_5\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 11.158
macrocell3 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/main_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active_split\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 2.910
macrocell2 U(3,1) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/main_8 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q 3.350
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\ \ADC_SAR_Seq:AMuxHw_2_Decoder_is_active\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_3\/main_0 16.109
macrocell43 U(2,5) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_3\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 110.705 MHz 9.033 32.634
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,4) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
Route 1 Net_954 Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 4.273
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 55.399 MHz 18.051 23.616
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 5.541
macrocell1 U(2,4) 1 Net_954 SETUP 3.510
Clock Skew 0.000
\ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_1 119.076 MHz 8.398 33.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \ControlReg:Sync:ctrl_reg\ \ControlReg:Sync:ctrl_reg\/busclk \ControlReg:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_938 \ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_1 2.308
macrocell80 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_in\ SETUP 3.510
Clock Skew 0.000
\ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/main_1 119.076 MHz 8.398 33.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \ControlReg:Sync:ctrl_reg\ \ControlReg:Sync:ctrl_reg\/busclk \ControlReg:Sync:ctrl_reg\/control_0 2.580
Route 1 Net_938 \ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/main_1 2.308
macrocell81 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_1 135.777 MHz 7.365 34.302
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_1 2.605
macrocell1 U(2,4) 1 Net_954 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 55.460 MHz 18.031 23.636
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 5.521
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 135.740 MHz 7.367 34.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 2.607
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ SETUP 3.510
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\ADC_SAR_Seq:bSAR_SEQ:soc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_3 3.553
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell81 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\ \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\ \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_3 2.303
macrocell80 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_in\ HOLD 0.000
Clock Skew 0.000
Net_954/q \ADC_SAR_Seq:bSAR_SEQ:EOCSts\/status_0 3.744
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,4) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
Route 1 Net_954 Net_954/q \ADC_SAR_Seq:bSAR_SEQ:EOCSts\/status_0 4.494
statuscell1 U(2,3) 1 \ADC_SAR_Seq:bSAR_SEQ:EOCSts\ HOLD -2.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_4 3.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_4 2.578
macrocell82 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/main_3 3.829
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell78 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q 1.250
macrocell78 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/q \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/main_3 2.579
macrocell78 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_1 4.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell82 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\ \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/q 1.250
macrocell82 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\ \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_1 2.775
macrocell82 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:soc_in\/q \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/main_1 4.040
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell80 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_in\ \ADC_SAR_Seq:bSAR_SEQ:soc_in\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:soc_in\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:soc_in\ \ADC_SAR_Seq:bSAR_SEQ:soc_in\/q \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\/main_1 2.790
macrocell78 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:is_soc_set\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:ChannelCounter\/count_6 \ADC_SAR_Seq:bSAR_SEQ:reset_fsm_reg\/main_8 4.257
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \ADC_SAR_Seq:bSAR_SEQ:ChannelCounter\ \ADC_SAR_Seq:bSAR_SEQ:ChannelCounter\/clock \ADC_SAR_Seq:bSAR_SEQ:ChannelCounter\/count_6 1.920
Route 1 \ADC_SAR_Seq:bSAR_SEQ:count_6\ \ADC_SAR_Seq:bSAR_SEQ:ChannelCounter\/count_6 \ADC_SAR_Seq:bSAR_SEQ:reset_fsm_reg\/main_8 2.337
macrocell79 U(3,2) 1 \ADC_SAR_Seq:bSAR_SEQ:reset_fsm_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:eoc_dbl_reg\/main_0 4.297
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,3) 1 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\ \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\ \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:eoc_dbl_reg\/main_0 3.047
macrocell76 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:eoc_dbl_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_2 4.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,3) 1 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\ \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\ \ADC_SAR_Seq:bSAR_SEQ:eoc_reg\/q \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\/main_2 3.051
macrocell82 U(3,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_src_select\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_14\/main_5 4.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell5 U(3,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\/clock_0 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\/q 1.250
Route 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\ \ADC_SAR_Seq:AMuxHw_2_Decoder_old_id_1\/q \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_14\/main_5 3.293
macrocell15 U(2,2) 1 \ADC_SAR_Seq:AMuxHw_2_Decoder_one_hot_14\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 5.523
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell1 U(2,4) 1 Net_954 Net_954/clock_0 Net_954/q 1.250
Route 1 Net_954 Net_954/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_0 4.273
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_1 3.855
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
Route 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q Net_954/main_1 2.605
macrocell1 U(2,4) 1 Net_954 HOLD 0.000
Clock Skew 0.000
\ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_1 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \ControlReg:Sync:ctrl_reg\ \ControlReg:Sync:ctrl_reg\/busclk \ControlReg:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_938 \ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_in\/main_1 2.308
macrocell80 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_in\ HOLD 0.000
Clock Skew 0.000
\ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/main_1 4.348
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(2,4) 1 \ControlReg:Sync:ctrl_reg\ \ControlReg:Sync:ctrl_reg\/busclk \ControlReg:Sync:ctrl_reg\/control_0 2.040
Route 1 Net_938 \ControlReg:Sync:ctrl_reg\/control_0 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\/main_1 2.308
macrocell81 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:soc_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 14.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout Net_954/main_2 5.541
macrocell1 U(2,4) 1 Net_954 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 3.857
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/clock_0 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q 1.250
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/q \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_1 2.607
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000
\ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 14.521
Type Location Fanout Instance/Net Source Dest Delay (ns)
drqcell4 [DrqHod=(0)][DrqId=(1)] 1 \ADC_SAR_Seq:FinalBuf\ \ADC_SAR_Seq:FinalBuf\/clock \ADC_SAR_Seq:FinalBuf\/termout 9.000
Route 1 \ADC_SAR_Seq:nrq\ \ADC_SAR_Seq:FinalBuf\/termout \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\/main_2 5.521
macrocell74 U(2,4) 1 \ADC_SAR_Seq:bSAR_SEQ:bus_clk_reg\ HOLD 0.000
Clock Skew 0.000