Static Timing Analysis

Project : 103-000-2011-00
Build Time : 01/04/16 17:15:12
Device : CY8C3666LTI-201
Temperature : 0C - 85/125C
VDDA : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 3.30
VDDIO2 : 5.00
VDDIO3 : 5.00
VDDOPAMP : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
ADC_Ext_CP_Clk ADC_Ext_CP_Clk 64.000 MHz 64.000 MHz N/A
ADC_Ext_CP_Clk(routed) ADC_Ext_CP_Clk(routed) 64.000 MHz 64.000 MHz N/A
ADC_theACLK(fixed-function) ADC_theACLK(fixed-function) 6.400 MHz 6.400 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 64.000 MHz 64.000 MHz 92.954 MHz
Clock_2 CyMASTER_CLK 5.000  Hz 5.000  Hz 70.666 MHz
DC_Motor_2_Clock_1 CyMASTER_CLK 32.000 MHz 32.000 MHz 40.999 MHz
DC_Motor_1_Clock_1 CyMASTER_CLK 32.000 MHz 32.000 MHz 39.755 MHz
EC_SPI_Clk CyMASTER_CLK 16.000 MHz 16.000 MHz 60.599 MHz
ADC_theACLK CyMASTER_CLK 6.400 MHz 6.400 MHz N/A
CyPLL_OUT CyPLL_OUT 64.000 MHz 64.000 MHz N/A
CyXTAL CyXTAL 10.000 MHz 10.000 MHz N/A
\ADC:DSM\/dec_clock \ADC:DSM\/dec_clock UNKNOWN UNKNOWN N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 2e+008ns(5  Hz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\EtherCAT_LED:datapath:u1\/z0_comb \EtherCAT_LED:datapath:u0\/cs_addr_0 70.666 MHz 14.151 199999985.849
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ \EtherCAT_LED:datapath:u1\/clock \EtherCAT_LED:datapath:u1\/z0_comb 2.700
Route 1 Net_395 \EtherCAT_LED:datapath:u1\/z0_comb Net_393/main_0 2.114
macrocell5 U(0,2) 1 Net_393 Net_393/main_0 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u0\/cs_addr_0 2.592
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ SETUP 4.400
Clock Skew 0.000
\EtherCAT_LED:datapath:u0\/z0_comb \EtherCAT_LED:datapath:u0\/cs_addr_0 70.726 MHz 14.139 199999985.861
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/z0_comb 2.700
Route 1 Net_394 \EtherCAT_LED:datapath:u0\/z0_comb Net_393/main_1 2.102
macrocell5 U(0,2) 1 Net_393 Net_393/main_1 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u0\/cs_addr_0 2.592
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ SETUP 4.400
Clock Skew 0.000
\EtherCAT_LED:datapath:u1\/z0_comb \EtherCAT_LED:datapath:u1\/cs_addr_0 70.811 MHz 14.122 199999985.878
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ \EtherCAT_LED:datapath:u1\/clock \EtherCAT_LED:datapath:u1\/z0_comb 2.700
Route 1 Net_395 \EtherCAT_LED:datapath:u1\/z0_comb Net_393/main_0 2.114
macrocell5 U(0,2) 1 Net_393 Net_393/main_0 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u1\/cs_addr_0 2.563
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ SETUP 4.400
Clock Skew 0.000
\EtherCAT_LED:datapath:u0\/z0_comb \EtherCAT_LED:datapath:u1\/cs_addr_0 70.872 MHz 14.110 199999985.890
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/z0_comb 2.700
Route 1 Net_394 \EtherCAT_LED:datapath:u0\/z0_comb Net_393/main_1 2.102
macrocell5 U(0,2) 1 Net_393 Net_393/main_1 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u1\/cs_addr_0 2.563
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ SETUP 4.400
Clock Skew 0.000
\EtherCAT_LED:datapath:u0\/sol_msb \EtherCAT_LED:datapath:u1\/sir 177.620 MHz 5.630 199999994.370
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/sol_msb 1.060
Route 1 \EtherCAT_LED:datapath:u0.sol_msb__sig\ \EtherCAT_LED:datapath:u0\/sol_msb \EtherCAT_LED:datapath:u1\/sir 0.000
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ SETUP 4.570
Clock Skew 0.000
Path Delay Requirement : 15.625ns(64 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
QR_1(0)_SYNC/out \DC_Motor_1:Status_Reg:sts:sts_reg\/status_0 92.954 MHz 10.758 4.867
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 1.040
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:Net_806\/main_1 2.680
macrocell16 U(3,2) 1 \DC_Motor_1:Net_806\ \DC_Motor_1:Net_806\/main_1 \DC_Motor_1:Net_806\/q 2.345
Route 1 \DC_Motor_1:Net_806\ \DC_Motor_1:Net_806\/q \DC_Motor_1:Status_Reg:sts:sts_reg\/status_0 3.594
statuscell1 U(2,2) 1 \DC_Motor_1:Status_Reg:sts:sts_reg\ SETUP 1.099
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:Status_Reg:sts:sts_reg\/status_1 107.898 MHz 9.268 6.357
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 1.040
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:Net_521\/main_1 2.680
macrocell17 U(3,2) 1 \DC_Motor_1:Net_521\ \DC_Motor_1:Net_521\/main_1 \DC_Motor_1:Net_521\/q 2.345
Route 1 \DC_Motor_1:Net_521\ \DC_Motor_1:Net_521\/q \DC_Motor_1:Status_Reg:sts:sts_reg\/status_1 2.104
statuscell1 U(2,2) 1 \DC_Motor_1:Status_Reg:sts:sts_reg\ SETUP 1.099
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\/main_2 122.684 MHz 8.151 7.474
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\/main_2 3.888
macrocell60 U(3,4) 1 \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\ SETUP 2.457
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\/main_3 125.156 MHz 7.990 7.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 1.040
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\/main_3 4.493
macrocell60 U(3,4) 1 \DC_Motor_1:PWM:PWMUDB:sc_kill_tmp\ SETUP 2.457
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:EdgeDetect_1:last\/main_0 125.156 MHz 7.990 7.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 1.040
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:EdgeDetect_1:last\/main_0 4.493
macrocell83 U(3,4) 1 \DC_Motor_1:EdgeDetect_1:last\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_0 132.013 MHz 7.575 8.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 1.806
Route 1 \DC_Motor_1:Index_Sign\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_0 3.312
macrocell37 U(2,2) 1 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_1:EdgeDetect_4:last\/main_0 132.013 MHz 7.575 8.050
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 1.806
Route 1 \DC_Motor_1:Index_Sign\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_1:EdgeDetect_4:last\/main_0 3.312
macrocell81 U(2,2) 1 \DC_Motor_1:EdgeDetect_4:last\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:prevCompare1\/main_1 138.122 MHz 7.240 8.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:prevCompare1\/main_1 2.977
macrocell62 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:prevCompare1\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:status_0\/main_2 138.122 MHz 7.240 8.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:status_0\/main_2 2.977
macrocell63 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:status_0\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:status_5\/main_0 138.122 MHz 7.240 8.385
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:status_5\/main_0 2.977
macrocell64 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:status_5\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 15.625ns(64 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
QR_2(0)_SYNC/out \DC_Motor_2:Status_Reg:sts:sts_reg\/status_0 97.248 MHz 10.283 5.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 1.040
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:Net_806\/main_1 2.765
macrocell28 U(3,3) 1 \DC_Motor_2:Net_806\ \DC_Motor_2:Net_806\/main_1 \DC_Motor_2:Net_806\/q 2.345
Route 1 \DC_Motor_2:Net_806\ \DC_Motor_2:Net_806\/q \DC_Motor_2:Status_Reg:sts:sts_reg\/status_0 3.034
statuscell2 U(3,2) 1 \DC_Motor_2:Status_Reg:sts:sts_reg\ SETUP 1.099
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:Status_Reg:sts:sts_reg\/status_1 100.634 MHz 9.937 5.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 1.040
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:Net_521\/main_1 2.765
macrocell29 U(3,3) 1 \DC_Motor_2:Net_521\ \DC_Motor_2:Net_521\/main_1 \DC_Motor_2:Net_521\/q 2.345
Route 1 \DC_Motor_2:Net_521\ \DC_Motor_2:Net_521\/q \DC_Motor_2:Status_Reg:sts:sts_reg\/status_1 2.688
statuscell2 U(3,2) 1 \DC_Motor_2:Status_Reg:sts:sts_reg\ SETUP 1.099
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_0 143.000 MHz 6.993 8.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 1.806
Route 1 \DC_Motor_2:Index_Sign\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_0 2.730
macrocell46 U(3,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_2:EdgeDetect_4:last\/main_0 143.000 MHz 6.993 8.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 1.806
Route 1 \DC_Motor_2:Index_Sign\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_3 \DC_Motor_2:EdgeDetect_4:last\/main_0 2.730
macrocell108 U(3,2) 1 \DC_Motor_2:EdgeDetect_4:last\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_4 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_1 143.246 MHz 6.981 8.644
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_4 1.806
Route 1 \DC_Motor_2:Enable_Index\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_4 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_1 2.718
macrocell46 U(3,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_2 149.813 MHz 6.675 8.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_2:Net_4218\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_2 2.412
macrocell87 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:status_0\/main_2 149.813 MHz 6.675 8.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_2:Net_4218\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:status_0\/main_2 2.412
macrocell90 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:status_0\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 Net_427/main_2 149.813 MHz 6.675 8.950
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_2:Net_4218\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 Net_427/main_2 2.412
macrocell92 U(2,3) 1 Net_427 SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:min_kill_reg\/main_1 149.993 MHz 6.667 8.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_2:Net_4218\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:min_kill_reg\/main_1 2.404
macrocell85 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:min_kill_reg\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_1 149.993 MHz 6.667 8.958
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 1.806
Route 1 \DC_Motor_2:Net_4218\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_1 2.404
macrocell88 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\ SETUP 2.457
Clock Skew 0.000
Path Delay Requirement : 15.625ns(64 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
EC_SOMI(0)_SYNC/out \EC_SPI:BSPIM:sR8:Dp:u0\/route_si 117.661 MHz 8.499 7.126
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 EC_SOMI(0)_SYNC EC_SOMI(0)_SYNC/clock EC_SOMI(0)_SYNC/out 1.040
Route 1 Net_979_SYNCOUT EC_SOMI(0)_SYNC/out \EC_SPI:BSPIM:sR8:Dp:u0\/route_si 2.709
datapathcell1 U(0,1) 1 \EC_SPI:BSPIM:sR8:Dp:u0\ SETUP 4.750
Clock Skew 0.000
Path Delay Requirement : 31.25ns(32 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 39.755 MHz 25.154 6.096
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 1.620
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.070
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:status_1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 5.708
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 40.660 MHz 24.594 6.656
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,2) 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/clock_0 \DC_Motor_1:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 7.963
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 41.384 MHz 24.164 7.086
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.700
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:status_1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 5.708
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 43.301 MHz 23.094 8.156
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 1.910
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.070
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:overflow\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_2 3.358
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_2 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 43.653 MHz 22.908 8.342
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell2 U(3,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 1.806
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:control_7\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.116
macrocell11 U(3,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.281
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 43.756 MHz 22.854 8.396
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 1.620
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.070
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:status_1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 5.708
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 43.773 MHz 22.845 8.405
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 1.620
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.070
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:status_1\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 5.708
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 3.042
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 44.855 MHz 22.294 8.956
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,2) 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/clock_0 \DC_Motor_1:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 7.963
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 3.051
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 44.873 MHz 22.285 8.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,2) 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/clock_0 \DC_Motor_1:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 7.963
macrocell7 U(1,4) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/main_0 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_0 3.042
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_1:QuadDec:Net_1203\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 44.956 MHz 22.244 9.006
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(3,5) 1 \DC_Motor_1:QuadDec:Net_1203\ \DC_Motor_1:QuadDec:Net_1203\/clock_0 \DC_Motor_1:QuadDec:Net_1203\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1203\ \DC_Motor_1:QuadDec:Net_1203\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 2.383
macrocell11 U(3,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 6.281
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
Path Delay Requirement : 31.25ns(32 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 40.999 MHz 24.391 6.859
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 1.806
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:control_7\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.136
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.744
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Net_1203\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 41.813 MHz 23.916 7.334
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell100 U(2,1) 1 \DC_Motor_2:QuadDec:Net_1203\ \DC_Motor_2:QuadDec:Net_1203\/clock_0 \DC_Motor_2:QuadDec:Net_1203\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Net_1203\ \DC_Motor_2:QuadDec:Net_1203\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 2.592
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.744
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 42.711 MHz 23.413 7.837
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell99 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\/clock_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_stored_i\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_1 2.089
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.744
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 44.617 MHz 22.413 8.837
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 1.910
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.ff0__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/ff0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ff0i \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb 2.070
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:overflow\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/f0_comb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_2 2.855
macrocell19 U(1,4) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_2 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.873
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 44.627 MHz 22.408 8.842
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell104 U(1,2) 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/clock_0 \DC_Motor_2:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_0 5.955
macrocell19 U(1,4) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.873
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 44.881 MHz 22.281 8.969
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 1.620
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.z0__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/z0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0i \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb 2.070
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:status_1\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/z0_comb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_1 3.013
macrocell19 U(1,4) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/main_1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:reload\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 2.873
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 6.800
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 3.560
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_1 45.263 MHz 22.093 9.157
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 1.806
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:control_7\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.136
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_1 7.746
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 45.267 MHz 22.091 9.159
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell5 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 1.806
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:control_7\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sCTRLReg:ctrlreg\/control_7 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 2.136
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_0 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/cs_addr_1 7.744
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ SETUP 8.060
Clock Skew 0.000
\DC_Motor_2:QuadDec:bQuadDec:state_0\/q \DC_Motor_2:QuadDec:Net_1251\/main_7 45.939 MHz 21.768 9.482
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell107 U(2,1) 1 \DC_Motor_2:QuadDec:bQuadDec:state_0\ \DC_Motor_2:QuadDec:bQuadDec:state_0\/clock_0 \DC_Motor_2:QuadDec:bQuadDec:state_0\/q 0.875
Route 1 \DC_Motor_2:QuadDec:bQuadDec:state_0\ \DC_Motor_2:QuadDec:bQuadDec:state_0\/q \DC_Motor_2:QuadDec:Net_1251_split\/main_6 10.102
macrocell84 U(1,5) 1 \DC_Motor_2:QuadDec:Net_1251_split\ \DC_Motor_2:QuadDec:Net_1251_split\/main_6 \DC_Motor_2:QuadDec:Net_1251_split\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Net_1251_split\ \DC_Motor_2:QuadDec:Net_1251_split\/q \DC_Motor_2:QuadDec:Net_1251\/main_7 5.989
macrocell93 U(2,5) 1 \DC_Motor_2:QuadDec:Net_1251\ SETUP 2.457
Clock Skew 0.000
\DC_Motor_2:QuadDec:Net_1203\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_1 46.258 MHz 21.618 9.632
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell100 U(2,1) 1 \DC_Motor_2:QuadDec:Net_1203\ \DC_Motor_2:QuadDec:Net_1203\/clock_0 \DC_Motor_2:QuadDec:Net_1203\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Net_1203\ \DC_Motor_2:QuadDec:Net_1203\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 2.592
macrocell23 U(2,1) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/main_2 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q 2.345
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:count_enable\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/cs_addr_1 7.746
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ SETUP 8.060
Clock Skew 0.000
Path Delay Requirement : 62.5ns(16 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\EC_SPI:BSPIM:BitCounter\/count_4 \EC_SPI:BSPIM:TxStsReg\/status_3 60.599 MHz 16.502 45.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_4 1.480
Route 1 \EC_SPI:BSPIM:count_4\ \EC_SPI:BSPIM:BitCounter\/count_4 \EC_SPI:BSPIM:load_rx_data\/main_0 5.918
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_0 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:TxStsReg\/status_3 5.660
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \EC_SPI:BSPIM:RxStsReg\/status_6 63.763 MHz 15.683 46.817
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,1) 1 \EC_SPI:BSPIM:sR8:Dp:u0\ \EC_SPI:BSPIM:sR8:Dp:u0\/clock \EC_SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb 3.700
Route 1 \EC_SPI:BSPIM:rx_status_4\ \EC_SPI:BSPIM:sR8:Dp:u0\/f1_blk_stat_comb \EC_SPI:BSPIM:rx_status_6\/main_5 6.414
macrocell4 U(0,3) 1 \EC_SPI:BSPIM:rx_status_6\ \EC_SPI:BSPIM:rx_status_6\/main_5 \EC_SPI:BSPIM:rx_status_6\/q 2.345
Route 1 \EC_SPI:BSPIM:rx_status_6\ \EC_SPI:BSPIM:rx_status_6\/q \EC_SPI:BSPIM:RxStsReg\/status_6 2.125
statusicell2 U(0,3) 1 \EC_SPI:BSPIM:RxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_4 \EC_SPI:BSPIM:sR8:Dp:u0\/f1_load 65.690 MHz 15.223 47.277
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_4 1.480
Route 1 \EC_SPI:BSPIM:count_4\ \EC_SPI:BSPIM:BitCounter\/count_4 \EC_SPI:BSPIM:load_rx_data\/main_0 5.918
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_0 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:sR8:Dp:u0\/f1_load 4.180
datapathcell1 U(0,1) 1 \EC_SPI:BSPIM:sR8:Dp:u0\ SETUP 1.300
Clock Skew 0.000
\EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:TxStsReg\/status_0 66.756 MHz 14.980 47.520
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(0,3) 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/clock_0 \EC_SPI:BSPIM:state_0\/q 0.875
Route 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:tx_status_0\/main_2 5.351
macrocell2 U(0,1) 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/main_2 \EC_SPI:BSPIM:tx_status_0\/q 2.345
Route 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/q \EC_SPI:BSPIM:TxStsReg\/status_0 5.310
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:state_1\/q \EC_SPI:BSPIM:TxStsReg\/status_0 67.426 MHz 14.831 47.669
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(0,1) 1 \EC_SPI:BSPIM:state_1\ \EC_SPI:BSPIM:state_1\/clock_0 \EC_SPI:BSPIM:state_1\/q 0.875
Route 1 \EC_SPI:BSPIM:state_1\ \EC_SPI:BSPIM:state_1\/q \EC_SPI:BSPIM:tx_status_0\/main_1 5.202
macrocell2 U(0,1) 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/main_1 \EC_SPI:BSPIM:tx_status_0\/q 2.345
Route 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/q \EC_SPI:BSPIM:TxStsReg\/status_0 5.310
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:state_2\/q \EC_SPI:BSPIM:TxStsReg\/status_0 69.633 MHz 14.361 48.139
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell50 U(0,1) 1 \EC_SPI:BSPIM:state_2\ \EC_SPI:BSPIM:state_2\/clock_0 \EC_SPI:BSPIM:state_2\/q 0.875
Route 1 \EC_SPI:BSPIM:state_2\ \EC_SPI:BSPIM:state_2\/q \EC_SPI:BSPIM:tx_status_0\/main_0 4.732
macrocell2 U(0,1) 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/main_0 \EC_SPI:BSPIM:tx_status_0\/q 2.345
Route 1 \EC_SPI:BSPIM:tx_status_0\ \EC_SPI:BSPIM:tx_status_0\/q \EC_SPI:BSPIM:TxStsReg\/status_0 5.310
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_2 \EC_SPI:BSPIM:TxStsReg\/status_3 74.979 MHz 13.337 49.163
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_2 1.480
Route 1 \EC_SPI:BSPIM:count_2\ \EC_SPI:BSPIM:BitCounter\/count_2 \EC_SPI:BSPIM:load_rx_data\/main_2 2.753
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_2 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:TxStsReg\/status_3 5.660
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_0 \EC_SPI:BSPIM:TxStsReg\/status_3 75.053 MHz 13.324 49.176
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_0 1.480
Route 1 \EC_SPI:BSPIM:count_0\ \EC_SPI:BSPIM:BitCounter\/count_0 \EC_SPI:BSPIM:load_rx_data\/main_4 2.740
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_4 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:TxStsReg\/status_3 5.660
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_3 \EC_SPI:BSPIM:TxStsReg\/status_3 75.994 MHz 13.159 49.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_3 1.480
Route 1 \EC_SPI:BSPIM:count_3\ \EC_SPI:BSPIM:BitCounter\/count_3 \EC_SPI:BSPIM:load_rx_data\/main_1 2.575
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_1 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:TxStsReg\/status_3 5.660
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_1 \EC_SPI:BSPIM:TxStsReg\/status_3 76.935 MHz 12.998 49.502
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_1 1.480
Route 1 \EC_SPI:BSPIM:count_1\ \EC_SPI:BSPIM:BitCounter\/count_1 \EC_SPI:BSPIM:load_rx_data\/main_3 2.414
macrocell1 U(0,1) 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/main_3 \EC_SPI:BSPIM:load_rx_data\/q 2.345
Route 1 \EC_SPI:BSPIM:load_rx_data\ \EC_SPI:BSPIM:load_rx_data\/q \EC_SPI:BSPIM:TxStsReg\/status_3 5.660
statusicell1 U(0,1) 1 \EC_SPI:BSPIM:TxStsReg\ SETUP 1.099
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\EtherCAT_LED:datapath:u0\/sol_msb \EtherCAT_LED:datapath:u1\/sir 0.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/sol_msb 0.870
Route 1 \EtherCAT_LED:datapath:u0.sol_msb__sig\ \EtherCAT_LED:datapath:u0\/sol_msb \EtherCAT_LED:datapath:u1\/sir 0.000
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ HOLD 0.000
Clock Skew 0.000
\EtherCAT_LED:datapath:u0\/z0_comb \EtherCAT_LED:datapath:u1\/cs_addr_0 9.300
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/z0_comb 2.290
Route 1 Net_394 \EtherCAT_LED:datapath:u0\/z0_comb Net_393/main_1 2.102
macrocell5 U(0,2) 1 Net_393 Net_393/main_1 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u1\/cs_addr_0 2.563
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ HOLD 0.000
Clock Skew 0.000
\EtherCAT_LED:datapath:u1\/z0_comb \EtherCAT_LED:datapath:u1\/cs_addr_0 9.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ \EtherCAT_LED:datapath:u1\/clock \EtherCAT_LED:datapath:u1\/z0_comb 2.290
Route 1 Net_395 \EtherCAT_LED:datapath:u1\/z0_comb Net_393/main_0 2.114
macrocell5 U(0,2) 1 Net_393 Net_393/main_0 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u1\/cs_addr_0 2.563
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ HOLD 0.000
Clock Skew 0.000
\EtherCAT_LED:datapath:u0\/z0_comb \EtherCAT_LED:datapath:u0\/cs_addr_0 9.329
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ \EtherCAT_LED:datapath:u0\/clock \EtherCAT_LED:datapath:u0\/z0_comb 2.290
Route 1 Net_394 \EtherCAT_LED:datapath:u0\/z0_comb Net_393/main_1 2.102
macrocell5 U(0,2) 1 Net_393 Net_393/main_1 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u0\/cs_addr_0 2.592
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ HOLD 0.000
Clock Skew 0.000
\EtherCAT_LED:datapath:u1\/z0_comb \EtherCAT_LED:datapath:u0\/cs_addr_0 9.341
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ \EtherCAT_LED:datapath:u1\/clock \EtherCAT_LED:datapath:u1\/z0_comb 2.290
Route 1 Net_395 \EtherCAT_LED:datapath:u1\/z0_comb Net_393/main_0 2.114
macrocell5 U(0,2) 1 Net_393 Net_393/main_0 Net_393/q 2.345
Route 1 Net_393 Net_393/q \EtherCAT_LED:datapath:u0\/cs_addr_0 2.592
datapathcell2 U(1,2) 1 \EtherCAT_LED:datapath:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
QA_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_0\/main_0 2.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,5) 1 QA_1(0)_SYNC QA_1(0)_SYNC/clock QA_1(0)_SYNC/out 0.700
Route 1 Net_415_SYNCOUT QA_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_0\/main_0 2.089
macrocell31 U(2,5) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_0\ HOLD 0.000
Clock Skew 0.000
QB_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_0\/main_0 2.808
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,5) 1 QB_1(0)_SYNC QB_1(0)_SYNC/clock QB_1(0)_SYNC/out 0.700
Route 1 Net_416_SYNCOUT QB_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_0\/main_0 2.108
macrocell34 U(0,5) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_0\ HOLD 0.000
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:min_kill_reg\/main_2 3.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 0.700
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:min_kill_reg\/main_2 2.680
macrocell58 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:min_kill_reg\ HOLD 0.000
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_2 3.380
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 0.700
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_2 2.680
macrocell61 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_4 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_1 3.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_4 1.428
Route 1 \DC_Motor_1:Enable_Index\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_4 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_1 2.110
macrocell37 U(2,2) 1 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:min_kill_reg\/main_1 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.428
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:min_kill_reg\/main_1 2.115
macrocell58 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:min_kill_reg\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_1 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 1.428
Route 1 \DC_Motor_1:Net_4218\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_5 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_1 2.115
macrocell61 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\ HOLD 0.000
Clock Skew 0.000
QI_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_2 4.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QI_1(0)_SYNC QI_1(0)_SYNC/clock QI_1(0)_SYNC/out 0.700
Route 1 Net_417_SYNCOUT QI_1(0)_SYNC/out \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\/main_2 3.490
macrocell37 U(2,2) 1 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_0\ HOLD 0.000
Clock Skew 0.000
QI_1(0)_SYNC/out \DC_Motor_1:EdgeDetect_4:last\/main_1 4.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QI_1(0)_SYNC QI_1(0)_SYNC/clock QI_1(0)_SYNC/out 0.700
Route 1 Net_417_SYNCOUT QI_1(0)_SYNC/out \DC_Motor_1:EdgeDetect_4:last\/main_1 3.490
macrocell81 U(2,2) 1 \DC_Motor_1:EdgeDetect_4:last\ HOLD 0.000
Clock Skew 0.000
QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:prevCompare1\/main_2 4.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,1) 1 QR_1(0)_SYNC QR_1(0)_SYNC/clock QR_1(0)_SYNC/out 0.700
Route 1 Net_418_SYNCOUT QR_1(0)_SYNC/out \DC_Motor_1:PWM:PWMUDB:prevCompare1\/main_2 3.590
macrocell62 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
QB_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:quad_B_delayed_0\/main_0 2.789
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 QB_2(0)_SYNC QB_2(0)_SYNC/clock QB_2(0)_SYNC/out 0.700
Route 1 Net_424_SYNCOUT QB_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:quad_B_delayed_0\/main_0 2.089
macrocell43 U(3,3) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_B_delayed_0\ HOLD 0.000
Clock Skew 0.000
QA_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/main_0 2.820
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,4) 1 QA_2(0)_SYNC QA_2(0)_SYNC/clock QA_2(0)_SYNC/out 0.700
Route 1 Net_423_SYNCOUT QA_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/main_0 2.120
macrocell40 U(0,4) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\ HOLD 0.000
Clock Skew 0.000
QI_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_2 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 QI_2(0)_SYNC QI_2(0)_SYNC/clock QI_2(0)_SYNC/out 0.700
Route 1 Net_425_SYNCOUT QI_2(0)_SYNC/out \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\/main_2 2.713
macrocell46 U(3,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_0\ HOLD 0.000
Clock Skew 0.000
QI_2(0)_SYNC/out \DC_Motor_2:EdgeDetect_4:last\/main_1 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(3,3) 1 QI_2(0)_SYNC QI_2(0)_SYNC/clock QI_2(0)_SYNC/out 0.700
Route 1 Net_425_SYNCOUT QI_2(0)_SYNC/out \DC_Motor_2:EdgeDetect_4:last\/main_1 2.713
macrocell108 U(3,2) 1 \DC_Motor_2:EdgeDetect_4:last\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:EdgeDetect_1:last\/main_0 3.465
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:EdgeDetect_1:last\/main_0 2.765
macrocell109 U(3,3) 1 \DC_Motor_2:EdgeDetect_1:last\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:min_kill_reg\/main_2 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:min_kill_reg\/main_2 2.917
macrocell85 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:min_kill_reg\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_2 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_2 2.917
macrocell88 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:prevCompare1\/main_2 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:prevCompare1\/main_2 2.917
macrocell89 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:status_5\/main_1 3.617
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:status_5\/main_1 2.917
macrocell91 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:status_5\ HOLD 0.000
Clock Skew 0.000
QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_3 3.626
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(2,3) 1 QR_2(0)_SYNC QR_2(0)_SYNC/clock QR_2(0)_SYNC/out 0.700
Route 1 Net_426_SYNCOUT QR_2(0)_SYNC/out \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_3 2.926
macrocell87 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
EC_SOMI(0)_SYNC/out \EC_SPI:BSPIM:sR8:Dp:u0\/route_si 3.409
Type Location Fanout Instance/Net Source Dest Delay (ns)
synccell U(0,2) 1 EC_SOMI(0)_SYNC EC_SOMI(0)_SYNC/clock EC_SOMI(0)_SYNC/out 0.700
Route 1 Net_979_SYNCOUT EC_SOMI(0)_SYNC/out \EC_SPI:BSPIM:sR8:Dp:u0\/route_si 2.709
datapathcell1 U(0,1) 1 \EC_SPI:BSPIM:sR8:Dp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\DC_Motor_1:PWM:PWMUDB:status_5\/q \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\/status_5 2.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell64 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:status_5\ \DC_Motor_1:PWM:PWMUDB:status_5\/clock_0 \DC_Motor_1:PWM:PWMUDB:status_5\/q 0.875
Route 1 \DC_Motor_1:PWM:PWMUDB:status_5\ \DC_Motor_1:PWM:PWMUDB:status_5\/q \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\/status_5 2.715
statusicell3 U(3,4) 1 \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\ HOLD -1.400
Clock Skew 0.000
\DC_Motor_1:PWM:PWMUDB:status_0\/q \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\/status_0 2.192
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell63 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:status_0\ \DC_Motor_1:PWM:PWMUDB:status_0\/clock_0 \DC_Motor_1:PWM:PWMUDB:status_0\/q 0.875
Route 1 \DC_Motor_1:PWM:PWMUDB:status_0\ \DC_Motor_1:PWM:PWMUDB:status_0\/q \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\/status_0 2.717
statusicell3 U(3,4) 1 \DC_Motor_1:PWM:PWMUDB:genblk8:stsreg\ HOLD -1.400
Clock Skew 0.000
\DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u1\/ci 2.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell4 U(3,1) 1 \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0\ \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0\/clock \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 2.250
Route 1 \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell5 U(2,1) 1 \DC_Motor_1:PWM:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 2.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell6 U(0,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 2.250
Route 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell7 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_2\/main_0 2.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,4) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\ \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/clock_0 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q 0.875
Route 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\ \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_2\/main_0 2.074
macrocell33 U(3,4) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_2\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q \DC_Motor_1:QuadDec:bQuadDec:quad_A_filt\/main_1 2.949
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell32 U(3,4) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\ \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/clock_0 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q 0.875
Route 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\ \DC_Motor_1:QuadDec:bQuadDec:quad_A_delayed_1\/q \DC_Motor_1:QuadDec:bQuadDec:quad_A_filt\/main_1 2.074
macrocell74 U(3,4) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_A_filt\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\/q \DC_Motor_1:QuadDec:bQuadDec:quad_B_filt\/main_2 2.957
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell36 U(2,5) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\ \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\/clock_0 \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\/q 0.875
Route 1 \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\ \DC_Motor_1:QuadDec:bQuadDec:quad_B_delayed_2\/q \DC_Motor_1:QuadDec:bQuadDec:quad_B_filt\/main_2 2.082
macrocell75 U(2,5) 1 \DC_Motor_1:QuadDec:bQuadDec:quad_B_filt\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/q \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_0 2.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell61 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\ \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/clock_0 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/q 0.875
macrocell61 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\ \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/q \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\/main_0 2.087
macrocell61 U(3,2) 1 \DC_Motor_1:PWM:PWMUDB:ltch_kill_reg\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:PWM:PWMUDB:prevCompare1\/q \DC_Motor_1:PWM:PWMUDB:status_0\/main_0 2.962
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell62 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:prevCompare1\ \DC_Motor_1:PWM:PWMUDB:prevCompare1\/clock_0 \DC_Motor_1:PWM:PWMUDB:prevCompare1\/q 0.875
Route 1 \DC_Motor_1:PWM:PWMUDB:prevCompare1\ \DC_Motor_1:PWM:PWMUDB:prevCompare1\/q \DC_Motor_1:PWM:PWMUDB:status_0\/main_0 2.087
macrocell63 U(3,3) 1 \DC_Motor_1:PWM:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\/q \DC_Motor_1:QuadDec:bQuadDec:index_filt\/main_2 2.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell39 U(1,3) 1 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\ \DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\/clock_0 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\/q 0.875
Route 1 \DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\ \DC_Motor_1:QuadDec:bQuadDec:index_delayed_2\/q \DC_Motor_1:QuadDec:bQuadDec:index_filt\/main_2 2.089
macrocell76 U(1,3) 1 \DC_Motor_1:QuadDec:bQuadDec:index_filt\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\DC_Motor_2:PWM:PWMUDB:status_5\/q \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\/status_5 2.196
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell91 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:status_5\ \DC_Motor_2:PWM:PWMUDB:status_5\/clock_0 \DC_Motor_2:PWM:PWMUDB:status_5\/q 0.875
Route 1 \DC_Motor_2:PWM:PWMUDB:status_5\ \DC_Motor_2:PWM:PWMUDB:status_5\/q \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\/status_5 2.721
statusicell6 U(2,4) 1 \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\ HOLD -1.400
Clock Skew 0.000
\DC_Motor_2:PWM:PWMUDB:status_0\/q \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\/status_0 2.203
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell90 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:status_0\ \DC_Motor_2:PWM:PWMUDB:status_0\/clock_0 \DC_Motor_2:PWM:PWMUDB:status_0\/q 0.875
Route 1 \DC_Motor_2:PWM:PWMUDB:status_0\ \DC_Motor_2:PWM:PWMUDB:status_0\/q \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\/status_0 2.728
statusicell6 U(2,4) 1 \DC_Motor_2:PWM:PWMUDB:genblk8:stsreg\ HOLD -1.400
Clock Skew 0.000
\DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u1\/ci 2.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(3,4) 1 \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0\ \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0\/clock \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb 2.250
Route 1 \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0.co_msb__sig\ \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u0\/co_msb \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u1\/ci 0.000
datapathcell9 U(2,4) 1 \DC_Motor_2:PWM:PWMUDB:sP16:pwmdp:u1\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 2.250
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(0,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/clock \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb 2.250
Route 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0.co_msb__sig\ \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u0\/co_msb \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\/ci 0.000
datapathcell11 U(1,3) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sC16:counterdp:u1\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/q \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_0 2.953
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell87 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\ \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/clock_0 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/q 0.875
macrocell87 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\ \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/q \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\/main_0 2.078
macrocell87 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:sc_kill_tmp\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/q \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_0 2.964
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell88 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\ \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/clock_0 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/q 0.875
macrocell88 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\ \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/q \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\/main_0 2.089
macrocell88 U(2,3) 1 \DC_Motor_2:PWM:PWMUDB:ltch_kill_reg\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q \DC_Motor_2:QuadDec:bQuadDec:index_delayed_2\/main_0 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(0,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\ \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/clock_0 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q 0.875
Route 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\ \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q \DC_Motor_2:QuadDec:bQuadDec:index_delayed_2\/main_0 2.090
macrocell48 U(0,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_2\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q \DC_Motor_2:QuadDec:bQuadDec:index_filt\/main_1 2.965
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell47 U(0,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\ \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/clock_0 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q 0.875
Route 1 \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\ \DC_Motor_2:QuadDec:bQuadDec:index_delayed_1\/q \DC_Motor_2:QuadDec:bQuadDec:index_filt\/main_1 2.090
macrocell103 U(0,2) 1 \DC_Motor_2:QuadDec:bQuadDec:index_filt\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\/q \DC_Motor_2:QuadDec:bQuadDec:quad_A_filt\/main_2 2.967
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell42 U(1,4) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\ \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\/clock_0 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\/q 0.875
Route 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\ \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_2\/q \DC_Motor_2:QuadDec:bQuadDec:quad_A_filt\/main_2 2.092
macrocell101 U(0,4) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_filt\ HOLD 0.000
Clock Skew 0.000
\DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/q \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_1\/main_0 2.971
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell40 U(0,4) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\ \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/clock_0 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/q 0.875
Route 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\ \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_0\/q \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_1\/main_0 2.096
macrocell41 U(0,4) 1 \DC_Motor_2:QuadDec:bQuadDec:quad_A_delayed_1\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\EC_SPI:BSPIM:load_cond\/q \EC_SPI:BSPIM:load_cond\/main_8 2.961
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(0,3) 1 \EC_SPI:BSPIM:load_cond\ \EC_SPI:BSPIM:load_cond\/clock_0 \EC_SPI:BSPIM:load_cond\/q 0.875
macrocell54 U(0,3) 1 \EC_SPI:BSPIM:load_cond\ \EC_SPI:BSPIM:load_cond\/q \EC_SPI:BSPIM:load_cond\/main_8 2.086
macrocell54 U(0,3) 1 \EC_SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:cnt_enable\/q \EC_SPI:BSPIM:cnt_enable\/main_3 2.983
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(0,4) 1 \EC_SPI:BSPIM:cnt_enable\ \EC_SPI:BSPIM:cnt_enable\/clock_0 \EC_SPI:BSPIM:cnt_enable\/q 0.875
macrocell56 U(0,4) 1 \EC_SPI:BSPIM:cnt_enable\ \EC_SPI:BSPIM:cnt_enable\/q \EC_SPI:BSPIM:cnt_enable\/main_3 2.108
macrocell56 U(0,4) 1 \EC_SPI:BSPIM:cnt_enable\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:state_0\/main_2 3.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(0,3) 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/clock_0 \EC_SPI:BSPIM:state_0\/q 0.875
macrocell52 U(0,3) 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:state_0\/main_2 2.431
macrocell52 U(0,3) 1 \EC_SPI:BSPIM:state_0\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:load_cond\/main_2 3.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(0,3) 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/clock_0 \EC_SPI:BSPIM:state_0\/q 0.875
Route 1 \EC_SPI:BSPIM:state_0\ \EC_SPI:BSPIM:state_0\/q \EC_SPI:BSPIM:load_cond\/main_2 2.431
macrocell54 U(0,3) 1 \EC_SPI:BSPIM:load_cond\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:state_2\/main_9 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/clock_0 \EC_SPI:BSPIM:ld_ident\/q 0.875
Route 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:state_2\/main_9 2.581
macrocell50 U(0,1) 1 \EC_SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:state_1\/main_9 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/clock_0 \EC_SPI:BSPIM:ld_ident\/q 0.875
Route 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:state_1\/main_9 2.581
macrocell51 U(0,1) 1 \EC_SPI:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:ld_ident\/main_8 3.456
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/clock_0 \EC_SPI:BSPIM:ld_ident\/q 0.875
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/q \EC_SPI:BSPIM:ld_ident\/main_8 2.581
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:ld_ident\/q Net_1413/main_10 3.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(0,1) 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/clock_0 \EC_SPI:BSPIM:ld_ident\/q 0.875
Route 1 \EC_SPI:BSPIM:ld_ident\ \EC_SPI:BSPIM:ld_ident\/q Net_1413/main_10 2.600
macrocell49 U(0,1) 1 Net_1413 HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_1 Net_1413/main_8 3.754
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_1 1.340
Route 1 \EC_SPI:BSPIM:count_1\ \EC_SPI:BSPIM:BitCounter\/count_1 Net_1413/main_8 2.414
macrocell49 U(0,1) 1 Net_1413 HOLD 0.000
Clock Skew 0.000
\EC_SPI:BSPIM:BitCounter\/count_1 \EC_SPI:BSPIM:state_2\/main_6 3.765
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,1) 1 \EC_SPI:BSPIM:BitCounter\ \EC_SPI:BSPIM:BitCounter\/clock \EC_SPI:BSPIM:BitCounter\/count_1 1.340
Route 1 \EC_SPI:BSPIM:count_1\ \EC_SPI:BSPIM:BitCounter\/count_1 \EC_SPI:BSPIM:state_2\/main_6 2.425
macrocell50 U(0,1) 1 \EC_SPI:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
+ Input To Output Section
Source Destination Delay (ns)
EC_SPI_IRQ(0)_PAD DIG_IO_0(0)_PAD 30.739
Type Location Fanout Instance/Net Source Dest Delay (ns)
\103-000-2011-00\ 1 EC_SPI_IRQ(0)_PAD EC_SPI_IRQ(0)_PAD EC_SPI_IRQ(0)_PAD 0.000
Route 1 EC_SPI_IRQ(0)_PAD EC_SPI_IRQ(0)_PAD EC_SPI_IRQ(0)/pad_in 0.000
iocell1 P12[7] 1 EC_SPI_IRQ(0) EC_SPI_IRQ(0)/pad_in EC_SPI_IRQ(0)/fb 7.303
Route 1 Net_440 EC_SPI_IRQ(0)/fb DIG_IO_0(0)/pin_input 7.808
iocell38 P3[2] 1 DIG_IO_0(0) DIG_IO_0(0)/pin_input DIG_IO_0(0)/pad_out 15.628
Route 1 DIG_IO_0(0)_PAD DIG_IO_0(0)/pad_out DIG_IO_0(0)_PAD 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
\EtherCAT_LED:datapath:u1\/so_comb AL_ERR(0)_PAD 27.025
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,2) 1 \EtherCAT_LED:datapath:u1\ \EtherCAT_LED:datapath:u1\/clock \EtherCAT_LED:datapath:u1\/so_comb 3.190
Route 1 Net_392 \EtherCAT_LED:datapath:u1\/so_comb AL_ERR(0)/pin_input 5.811
iocell10 P15[6] 1 AL_ERR(0) AL_ERR(0)/pin_input AL_ERR(0)/pad_out 18.024
Route 1 AL_ERR(0)_PAD AL_ERR(0)/pad_out AL_ERR(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK
Source Destination Delay (ns)
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_0 Direction_1(0)_PAD 25.066
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_0 1.806
Route 1 Net_420 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_0 Direction_1(0)/pin_input 7.326
iocell27 P3[1] 1 Direction_1(0) Direction_1(0)/pin_input Direction_1(0)/pad_out 15.934
Route 1 Direction_1(0)_PAD Direction_1(0)/pad_out Direction_1(0)_PAD 0.000
Clock Clock path delay 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_0 Direction_2(0)_PAD 24.910
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_0 1.806
Route 1 Net_428 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_0 Direction_2(0)/pin_input 7.297
iocell34 P15[5] 1 Direction_2(0) Direction_2(0)/pin_input Direction_2(0)/pad_out 15.807
Route 1 Direction_2(0)_PAD Direction_2(0)/pad_out Direction_2(0)_PAD 0.000
Clock Clock path delay 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_1 Sleep_1(0)_PAD 24.662
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_1 1.806
Route 1 Net_421 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_1 Sleep_1(0)/pin_input 6.758
iocell28 P0[5] 1 Sleep_1(0) Sleep_1(0)/pin_input Sleep_1(0)/pad_out 16.098
Route 1 Sleep_1(0)_PAD Sleep_1(0)/pad_out Sleep_1(0)_PAD 0.000
Clock Clock path delay 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_2 Mode_2(0)_PAD 24.388
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_2 1.806
Route 1 Net_430 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_2 Mode_2(0)/pin_input 7.414
iocell36 P2[0] 1 Mode_2(0) Mode_2(0)/pin_input Mode_2(0)/pad_out 15.168
Route 1 Mode_2(0)_PAD Mode_2(0)/pad_out Mode_2(0)_PAD 0.000
Clock Clock path delay 0.000
\DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_1 Sleep_2(0)_PAD 24.135
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell6 U(2,3) 1 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\ \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_1 1.806
Route 1 Net_429 \DC_Motor_2:Control_Reg:Sync:ctrl_reg\/control_1 Sleep_2(0)/pin_input 7.018
iocell35 P15[4] 1 Sleep_2(0) Sleep_2(0)/pin_input Sleep_2(0)/pad_out 15.311
Route 1 Sleep_2(0)_PAD Sleep_2(0)/pad_out Sleep_2(0)_PAD 0.000
Clock Clock path delay 0.000
\DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_2 Mode_1(0)_PAD 23.996
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell3 U(3,2) 1 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\ \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/busclk \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_2 1.806
Route 1 Net_422 \DC_Motor_1:Control_Reg:Sync:ctrl_reg\/control_2 Mode_1(0)/pin_input 6.541
iocell37 P3[0] 1 Mode_1(0) Mode_1(0)/pin_input Mode_1(0)/pad_out 15.649
Route 1 Mode_1(0)_PAD Mode_1(0)/pad_out Mode_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ DC_Motor_1_Clock_1
Source Destination Delay (ns)
Net_419/q PWM_1(0)_PAD 23.068
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell65 U(3,3) 1 Net_419 Net_419/clock_0 Net_419/q 0.875
Route 1 Net_419 Net_419/q PWM_1(0)/pin_input 6.349
iocell26 P0[4] 1 PWM_1(0) PWM_1(0)/pin_input PWM_1(0)/pad_out 15.844
Route 1 PWM_1(0)_PAD PWM_1(0)/pad_out PWM_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ DC_Motor_2_Clock_1
Source Destination Delay (ns)
Net_427/q PWM_2(0)_PAD 24.099
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell92 U(2,3) 1 Net_427 Net_427/clock_0 Net_427/q 0.875
Route 1 Net_427 Net_427/q PWM_2(0)/pin_input 7.530
iocell33 P2[6] 1 PWM_2(0) PWM_2(0)/pin_input PWM_2(0)/pad_out 15.694
Route 1 PWM_2(0)_PAD PWM_2(0)/pad_out PWM_2(0)_PAD 0.000
Clock Clock path delay 0.000
+ EC_SPI_Clk
Source Destination Delay (ns)
Net_978/q EC_CS(0)_PAD 24.158
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(3,1) 1 Net_978 Net_978/clock_0 Net_978/q 0.875
Route 1 Net_978 Net_978/q EC_CS(0)/pin_input 7.491
iocell7 P1[4] 1 EC_CS(0) EC_CS(0)/pin_input EC_CS(0)/pad_out 15.792
Route 1 EC_CS(0)_PAD EC_CS(0)/pad_out EC_CS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_976/q EC_SCLK(0)_PAD 23.072
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell57 U(0,4) 1 Net_976 Net_976/clock_0 Net_976/q 0.875
Route 1 Net_976 Net_976/q EC_SCLK(0)/pin_input 6.206
iocell8 P12[6] 1 EC_SCLK(0) EC_SCLK(0)/pin_input EC_SCLK(0)/pad_out 15.991
Route 1 EC_SCLK(0)_PAD EC_SCLK(0)/pad_out EC_SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_978/q DIG_IO_5(0)_PAD 22.750
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(3,1) 1 Net_978 Net_978/clock_0 Net_978/q 0.875
Route 1 Net_978 Net_978/q DIG_IO_5(0)/pin_input 5.999
iocell11 P3[5] 1 DIG_IO_5(0) DIG_IO_5(0)/pin_input DIG_IO_5(0)/pad_out 15.876
Route 1 DIG_IO_5(0)_PAD DIG_IO_5(0)/pad_out DIG_IO_5(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1413/q EC_MOSI(0)_PAD 22.292
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell49 U(0,1) 1 Net_1413 Net_1413/clock_0 Net_1413/q 0.875
Route 1 Net_1413 Net_1413/q EC_MOSI(0)/pin_input 5.853
iocell9 P1[5] 1 EC_MOSI(0) EC_MOSI(0)/pin_input EC_MOSI(0)/pad_out 15.564
Route 1 EC_MOSI(0)_PAD EC_MOSI(0)/pad_out EC_MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
+ Asynchronous Constraints
+ Recovery
Path Delay Requirement : 31.25ns(32 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 88.921 MHz 11.246 20.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,2) 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/clock_0 \DC_Motor_1:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 10.371
statusicell4 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
Path Delay Requirement : 31.25ns(32 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 235.571 MHz 4.245 27.005
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell104 U(1,2) 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/clock_0 \DC_Motor_2:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 3.370
statusicell7 U(1,2) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ RECOVERY -0.000
Clock Skew 0.000
+ Removal
Source Destination Slack (ns) Violation
\DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 11.246
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell77 U(2,2) 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/clock_0 \DC_Motor_1:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_1:QuadDec:Net_1260\ \DC_Motor_1:QuadDec:Net_1260\/q \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 10.371
statusicell4 U(1,5) 1 \DC_Motor_1:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 4.245
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell104 U(1,2) 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/clock_0 \DC_Motor_2:QuadDec:Net_1260\/q 0.875
Route 1 \DC_Motor_2:QuadDec:Net_1260\ \DC_Motor_2:QuadDec:Net_1260\/q \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\/reset 3.370
statusicell7 U(1,2) 1 \DC_Motor_2:QuadDec:Cnt16:CounterUDB:sSTSReg:stsreg\ REMOVAL 0.000
Clock Skew 0.000