Static Timing Analysis

Project : SR_FlipFlop
Build Time : 08/09/12 20:37:31
Device : CY8C5568AXI-060
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
Pin_1(0)/fb Pin_2(0)_PAD 48.494
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P6[1] 1 Pin_1(0) Pin_1(0)/clock Pin_1(0)/fb 18.426
Route 1 Net_27 Pin_1(0)/fb Net_26/main_2 4.675
macrocell1 U(0,1) 1 Net_26 Net_26/main_2 Net_26/q 3.350
Route 1 Net_26 Net_26/q Pin_2(0)/pin_input 5.801
iocell2 P6[3] 1 Pin_2(0) Pin_2(0)/pin_input Pin_2(0)/pad_out 16.242
Route 1 Pin_2(0)_PAD Pin_2(0)/pad_out Pin_2(0)_PAD 0.000
Clock Clock path delay 0.000