Static Timing Analysis

Project : Test
Build Time : 08/11/12 19:35:20
Device : CY8C5568AXI-060
Temperature : -40C - 85C
Vio0 : 5.0
Vio1 : 5.0
Vio2 : 5.0
Vio3 : 5.0
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Type Nominal Frequency Required Frequency Maximum Frequency Violation
ClockBlock/clk_bus Async 24.000 MHz 24.000 MHz N/A
CyBUS_CLK Sync 24.000 MHz 24.000 MHz N/A
CyILO Async 1.000 kHz 1.000 kHz N/A
CyIMO Async 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK Sync 24.000 MHz 24.000 MHz N/A
CyPLL_OUT Async 24.000 MHz 24.000 MHz N/A
+ Clock To Output Section
+ CyBUS_CLK
Source Destination Delay (ns)
\Control_Reg_1:ctrl_reg\/control_2 Pin_1(0)_PAD 49.343
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(3,1) 1 \Control_Reg_1:ctrl_reg\ \Control_Reg_1:ctrl_reg\/busclk \Control_Reg_1:ctrl_reg\/control_2 2.580
Route 1 Net_39 \Control_Reg_1:ctrl_reg\/control_2 \JK_Latch_1:a1\/main_2 2.800
macrocell4 U(3,1) 1 \JK_Latch_1:a1\ \JK_Latch_1:a1\/main_2 \JK_Latch_1:a1\/q 3.350
Route 1 \JK_Latch_1:a1\ \JK_Latch_1:a1\/q \JK_Latch_1:b1\/main_0 2.292
macrocell5 U(3,1) 1 \JK_Latch_1:b1\ \JK_Latch_1:b1\/main_0 \JK_Latch_1:b1\/q 3.350
Route 1 \JK_Latch_1:b1\ \JK_Latch_1:b1\/q \JK_Latch_1:c1\/main_1 2.314
macrocell6 U(3,1) 1 \JK_Latch_1:c1\ \JK_Latch_1:c1\/main_1 \JK_Latch_1:c1\/q 3.350
Route 1 \JK_Latch_1:c1\ \JK_Latch_1:c1\/q Net_37/main_1 2.305
macrocell1 U(3,1) 1 Net_37 Net_37/main_1 Net_37/q 3.350
Route 1 Net_37 Net_37/q Pin_1(0)/pin_input 7.410
iocell1 P6[3] 1 Pin_1(0) Pin_1(0)/pin_input Pin_1(0)/pad_out 16.242
Route 1 Pin_1(0)_PAD Pin_1(0)/pad_out Pin_1(0)_PAD 0.000
Clock Clock path delay 0.000