Static Timing Analysis

Project : CAN_Full_Example01
Build Time : 04/23/17 09:47:39
Device : CY8C5888LTI-LP097
Temperature : -40C - 85/125C
VDDA : 3.30
VDDABUF : 3.30
VDDD : 3.30
VDDIO0 : 3.30
VDDIO1 : 3.30
VDDIO2 : 3.30
VDDIO3 : 3.30
VUSB : 3.30
Voltage : 3.3
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 62.988 MHz
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 55.822 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 62.988 MHz 15.876 25.791
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.675
macrocell6 U(1,3) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(1,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 86.851 MHz 11.514 30.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.912
macrocell18 U(1,4) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 86.851 MHz 11.514 30.153
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.912
macrocell23 U(1,4) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 86.957 MHz 11.500 30.167
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.898
macrocell15 U(1,4) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 86.964 MHz 11.499 30.168
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.897
macrocell24 U(0,4) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 97.305 MHz 10.277 31.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.675
macrocell21 U(1,3) 1 \UART_1:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 97.305 MHz 10.277 31.390
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.675
macrocell22 U(1,3) 1 \UART_1:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 55.822 MHz 17.914 1065.419
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell12 U(1,3) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_3 4.822
macrocell2 U(0,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.151 MHz 16.353 1066.980
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell11 U(0,3) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.261
macrocell2 U(0,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.767 MHz 16.190 1067.143
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell10 U(1,3) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.098
macrocell2 U(0,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 62.582 MHz 15.979 1067.354
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell15 U(1,4) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 3.704
macrocell5 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_state_3\/q \UART_1:BUART:sRX:RxBitCounter\/load 62.980 MHz 15.878 1067.455
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell17 U(1,4) 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/clock_0 \UART_1:BUART:rx_state_3\/q 1.250
Route 1 \UART_1:BUART:rx_state_3\ \UART_1:BUART:rx_state_3\/q \UART_1:BUART:rx_counter_load\/main_2 3.603
macrocell5 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_2 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 63.199 MHz 15.823 1067.510
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell14 U(1,3) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 3.548
macrocell5 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 63.975 MHz 15.631 1067.702
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg 0.190
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce0_reg \UART_1:BUART:counter_load_not\/main_2 3.599
macrocell2 U(0,3) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.302
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_2\/q \UART_1:BUART:sRX:RxBitCounter\/load 66.503 MHz 15.037 1068.296
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell18 U(1,4) 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/clock_0 \UART_1:BUART:rx_state_2\/q 1.250
Route 1 \UART_1:BUART:rx_state_2\ \UART_1:BUART:rx_state_2\/q \UART_1:BUART:rx_counter_load\/main_3 2.762
macrocell5 U(1,4) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_3 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.315
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 69.113 MHz 14.469 1068.864
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(0,4) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_3 4.102
macrocell3 U(0,3) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_3 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 2.937
statusicell1 U(0,4) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:pollcount_0\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 73.932 MHz 13.526 1069.807
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell22 U(1,3) 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/clock_0 \UART_1:BUART:pollcount_0\/q 1.250
Route 1 \UART_1:BUART:pollcount_0\ \UART_1:BUART:pollcount_0\/q \UART_1:BUART:rx_postpoll\/main_2 3.167
macrocell6 U(1,3) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_2 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(1,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 6.767
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:pollcount_1\/main_3 4.675
macrocell21 U(1,3) 1 \UART_1:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 6.767
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:pollcount_0\/main_2 4.675
macrocell22 U(1,3) 1 \UART_1:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 7.989
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.897
macrocell24 U(0,4) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 7.990
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_9 5.898
macrocell15 U(1,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 8.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_8 5.912
macrocell18 U(1,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 8.004
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_6 5.912
macrocell23 U(1,4) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 12.406
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell2 P15[5] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.092
Route 1 Net_15 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_1 4.675
macrocell6 U(1,3) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_1 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.289
datapathcell3 U(1,3) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.146
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell23 U(1,4) 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/clock_0 \UART_1:BUART:rx_status_3\/q 1.250
Route 1 \UART_1:BUART:rx_status_3\ \UART_1:BUART:rx_status_3\/q \UART_1:BUART:sRX:RxSts\/status_3 2.896
statusicell2 U(0,3) 1 \UART_1:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_1\/main_4 2.798
macrocell10 U(1,3) 1 \UART_1:BUART:tx_state_1\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.988
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:tx_state_2\/main_4 2.798
macrocell12 U(1,3) 1 \UART_1:BUART:tx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 3.003
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(0,3) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg 0.190
Route 1 \UART_1:BUART:tx_counter_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/ce1_reg \UART_1:BUART:txn\/main_5 2.813
macrocell9 U(0,3) 1 \UART_1:BUART:txn\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 3.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.612
macrocell16 U(1,4) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 3.232
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_2\/main_6 2.612
macrocell18 U(1,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 3.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_6 2.622
macrocell15 U(1,4) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 3.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 \UART_1:BUART:rx_count_5\ \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_3\/main_6 2.622
macrocell17 U(1,4) 1 \UART_1:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 3.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.640
macrocell16 U(1,4) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 3.260
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,4) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_1:BUART:rx_count_4\ \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_2\/main_7 2.640
macrocell18 U(1,4) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
+ Clock To Output Section
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 28.181
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell9 U(0,3) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_7/main_0 2.288
macrocell1 U(0,3) 1 Net_7 Net_7/main_0 Net_7/q 3.350
Route 1 Net_7 Net_7/q Tx_1(0)/pin_input 5.445
iocell3 P15[4] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 15.848
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000