Static Timing Analysis

Project : PLC_XBEE
Build Time : 05/15/15 11:46:13
Device : CY8C4245AXI-483
Temperature : -40C - 85C
VDDA : 3.30
VDDD : 3.30
Voltage : 3.3
Expand All | Collapse All | Show All Paths | Hide All Paths
+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyHFCLK CyHFCLK 24.000 MHz 24.000 MHz N/A
PLC_UART_SCBCLK CyHFCLK 125.000 kHz 125.000 kHz N/A
XBEE_UART_SCBCLK CyHFCLK 461.538 kHz 461.538 kHz N/A
CyILO CyILO 32.000 kHz 32.000 kHz N/A
CyIMO CyIMO 24.000 MHz 24.000 MHz N/A
CyLFCLK CyLFCLK 32.000 kHz 32.000 kHz N/A
CySYSCLK CySYSCLK 24.000 MHz 24.000 MHz N/A
PLC_UART_SCBCLK(FFB) PLC_UART_SCBCLK(FFB) 125.000 kHz 125.000 kHz N/A
XBEE_UART_SCBCLK(FFB) XBEE_UART_SCBCLK(FFB) 461.538 kHz 461.538 kHz N/A